Commits · d092dd56aed8af64425446544ca7c9a0616d86ce · Roger Ferrer / llvm-epi · GitLab

May 11, 2021
- [RISCV] Regenerate stepvector.ll. NFC · d092dd56
  Craig Topper authored May 11, 2021
  d092dd56
- [PowerPC] Improve codegen for int-to-fp conversion of subword vector extract · ffbffaf6
  Albion Fung authored May 11, 2021
  ffbffaf6
- [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. · 69069509
  Amara Emerson authored May 10, 2021
  69069509
- [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. · ae2b36e8
  Amara Emerson authored Jan 24, 2021
  ae2b36e8
- [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local · ec27c5f1
  Fangrui Song authored May 11, 2021
  ec27c5f1
- [X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) ->... · 4f80340f
  Simon Pilgrim authored May 11, 2021
  4f80340f
- [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min. · ce6e4f27
  Craig Topper authored May 11, 2021
  ce6e4f27
- [X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32) · 5f78ba00
  Roman Lebedev authored May 11, 2021
  5f78ba00
- [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. · dc00cbb5
  Craig Topper authored May 10, 2021
  dc00cbb5
- [NFC][X86] Precommit another testcase for D101944 · 2c1f9f39
  Roman Lebedev authored May 11, 2021
  
  2c1f9f39
- [X86][SSE] Replace foldShuffleOfHorizOp with generalized version in... · 9acc03ad
  Simon Pilgrim authored May 11, 2021
  9acc03ad
- [AMDGPU] Move code sinking before structurizer · 09fe84ab
  Piotr Sobczak authored May 11, 2021
  09fe84ab
- [PowerPC][Bug] Fix Bug in Stack Frame Update Code · c79bc594
  Stefan Pintilie authored May 11, 2021
  c79bc594
- [RegAllocFast] properly handle STATEPOINT instruction. · df47368d
  Denis Antrushin authored Mar 24, 2021
  df47368d
- [AMDGPU] Add some GFX10.3 testing. NFC. · 3b873831
  Jay Foad authored May 11, 2021
  
  3b873831
- [CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols · b2f21b14
  Andy Wingo authored May 05, 2021
  b2f21b14
- [WebAssembly] Support for WebAssembly globals in LLVM IR · d7086af2
  Paulo Matos authored May 04, 2021
  d7086af2
- [AMDGPU] Pre-commit tests for D102211 · ad558a4f
  Carl Ritson authored May 11, 2021
  
  ad558a4f
- [RISCV] Fix the calculation of the offset of Zvlsseg spilling. · d8ec2b18
  Hsiangkai Wang authored May 10, 2021
  d8ec2b18
- [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps · 79be9c59
  Jessica Paquette authored May 03, 2021
  79be9c59
- [AArch64][GlobalISel] Enable memcpy family combines on minsize functions · 6d8b070d
  Jessica Paquette authored May 10, 2021
  6d8b070d
May 10, 2021
- Pre-commit test case for D101970 · a0fed635
  Guozhi Wei authored May 10, 2021
  a0fed635
- [Hexagon] Handle loads and stores of scalar predicate vectors · 8b9c15c2
  Krzysztof Parzyszek authored May 10, 2021
  8b9c15c2
- [test] Put aix-xcoff-huge-relocs.ll under expensive checks · edfa44b7
  Arthur Eubanks authored May 10, 2021
  edfa44b7
- [VecLib] Add support for vector fns from Darwin's libsystem. · 93a9a8a8
  Florian Hahn authored May 10, 2021
  93a9a8a8
- [PowerPC] Spilling to registers does not require frame index scavenging · 6215f49b
  Stefan Pintilie authored May 10, 2021
  6215f49b
- [TargetLowering] Only inspect attributes in the arguments for ArgListEntry · 16748bd2
  Arthur Eubanks authored May 03, 2021
  16748bd2
- [GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges. · dc754999
  Amara Emerson authored May 10, 2021
  dc754999
- [X86][AVX] Add example of failure to remove a 256-bit... · a9196db9
  Simon Pilgrim authored May 10, 2021
  a9196db9
- [X86][SSE] Add examples of failures to remove a permute(pack(pack(),pack()))... · 22f83421
  Simon Pilgrim authored May 10, 2021
  22f83421
- [RISCV] Correct VL for fixed length masked scatter. · 80b95108
  Craig Topper authored May 10, 2021
  80b95108
- [X86][SSE] Add tests for missing shuffle(pack(x,y),pack(z,w)) -> permute(pack()) folds. · 1d802e16
  Simon Pilgrim authored May 10, 2021
  
  1d802e16
- [X86][SSE] Merge equal X32/X64 check prefixes. NFCI. · b483c0af
  Simon Pilgrim authored May 10, 2021
  
  b483c0af
- [X86] Fix position-independent TType encoding · b0ef2070
  Harald van Dijk authored May 10, 2021
  b0ef2070
- [clang][AArch32] Correctly align HA arguments when passed on the stack · 5c7b43aa
  Momchil Velikov authored May 10, 2021
  5c7b43aa
- [PowerPC] Enable safe for 32bit vins* P10 instructions · 0c41f778
  Zarko Todorovski authored May 10, 2021
  0c41f778
- [AArch64][SVE] Improve SVE codegen for fixed length BITCAST · 635164b9
  Bradley Smith authored May 06, 2021
  635164b9
- [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics · 65c89cd1
  Bradley Smith authored Apr 30, 2021
  65c89cd1
- [AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics · f8f953c2
  Bradley Smith authored Apr 30, 2021
  f8f953c2
- [AArch64][SVE] Fix isel failure for FP-extending loads · 407a3388
  Sander de Smalen authored May 10, 2021
  407a3388