Commits · d157a9bc8ba1085cc4808c6941412322a7fd884e · Roger Ferrer / llvm-epi · GitLab

Oct 28, 2019
- Add Windows Control Flow Guard checks (/guard:cf). · d157a9bc
  Andrew Paverd authored Oct 28, 2019
  d157a9bc
- Precommit AArch64 test for -consider-local-interval-cost · 265ddc57
  Sanne Wouda authored Oct 28, 2019
  265ddc57
- [DebugInfo] MachineSink: find more DBG_VALUEs to sink · f5e1b718
  Jeremy Morse authored Oct 28, 2019
  f5e1b718
- [DAGCombiner] widen any_ext of popcount based on target support · 1ebd4a2e
  Sanjay Patel authored Oct 28, 2019
  1ebd4a2e
- [InstCombine][NFC] Tests for uadd.sat and sadd.sat canonicalisation. · d2ec416c
  David Green authored Oct 21, 2019
  
  d2ec416c
- [CVP] prevent propagating poison when substituting edge values into a phi (PR43802) · f2e93d10
  Sanjay Patel authored Oct 28, 2019
  f2e93d10
- [DebugInfo] MachineSink: Insert undef DBG_VALUEs when sinking instructions · ee50590e
  Jeremy Morse authored Oct 28, 2019
  ee50590e
- [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64 · b8042dbe
  Dmitry Preobrazhensky authored Oct 28, 2019
  b8042dbe
- [Codegen][ARM] Add float softening for cbrt · ba2c6255
  David Green authored Oct 23, 2019
  ba2c6255
- [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLE · f6e11a36
  vhscampos authored Oct 17, 2019
  f6e11a36
- [AArch64][SVE] Implement masked load intrinsics · da720a38
  Kerry McLaughlin authored Oct 28, 2019
  da720a38
- [RISCV] Lower llvm.trap and llvm.debugtrap · 7214f7a7
  Sam Elliott authored Oct 28, 2019
  7214f7a7
- [llvm-objcopy][MachO] Implement --only-section · 7f19dd1e
  Seiya Nuta authored Oct 28, 2019
  7f19dd1e
- [X86] Fix 48/96 byte memcmp code gen · 657e4240
  David Zarzycki authored Oct 26, 2019
  657e4240
- [X86] Use 64-bit version of source register in LowerPATCHABLE_EVENT_CALL and... · 7af8d526
  Craig Topper authored Oct 27, 2019
  7af8d526
Oct 27, 2019
- [SDAG] fold insert_vector_elt with undef index · 85a2146c
  Sanjay Patel authored Oct 27, 2019
  85a2146c
- [LegalizeTypes] When promoting BITREVERSE/BSWAP don't take the shift amount... · f067dd83
  Craig Topper authored Oct 27, 2019
  f067dd83
Oct 26, 2019
- [X86] Prefer KORTEST on Knights Landing or later for memcmp() · 11c92020
  David Zarzycki authored Oct 17, 2019
  11c92020
- [X86] NFC: expand inline memcmp test coverage · 0d050938
  David Zarzycki authored Oct 20, 2019
  0d050938
- [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. · e921ede5
  cdevadas authored Oct 26, 2019
  e921ede5
- [SDAG] fold extract_vector_elt with undef index · 4c476176
  Sanjay Patel authored Oct 25, 2019
  4c476176
- [AMDGPU] Enable SGPR copy folding · 4c0251da
  Stanislav Mekhanoshin authored Oct 25, 2019
  4c0251da
Oct 25, 2019
- [BPF] fix a CO-RE issue with -mattr=+alu32 · a27c998c
  Yonghong Song authored Oct 24, 2019
  a27c998c
- [x86] add tests for extractelement with undef index (PR42689); NFC · e070cf81
  Sanjay Patel authored Oct 25, 2019
  
  e070cf81
- Revert "[ARM] Uses "Sun Style" syntax for section switching" · a6b0219f
  Jian Cai authored Oct 25, 2019
  a6b0219f
- GlobalISel: Implement widenScalar for G_INSERT_VECTOR_ELT · 1a276d1e
  Matt Arsenault authored Oct 01, 2019
  
  1a276d1e
- [ARM] Uses "Sun Style" syntax for section switching · 03de2f84
  Jian Cai authored Oct 25, 2019
  03de2f84
- AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG · 171cf530
  Matt Arsenault authored Oct 08, 2019
  171cf530
- AMDGPU: Fix the broken dominator tree when creating waterfall loop for resource descriptor · 1ce552f3
  Changpeng Fang authored Oct 25, 2019
  1ce552f3
- [gicombiner] Add parse failure tests for defs/match · a6e1de4a
  Daniel Sanders authored Oct 03, 2019
  
  a6e1de4a
- Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs." · 64c1f660
  Amy Huang authored Oct 25, 2019
  64c1f660
- [LLD][ThinLTO] Handle GUID collision in import global processing · cc0b9647
  Teresa Johnson authored Oct 25, 2019
  cc0b9647
- [CVP] add test for poison propagation bug (PR43802); NFC · 3c7c3717
  Sanjay Patel authored Oct 25, 2019
  
  3c7c3717
- [llvm-objcopy][MachO] Add support for min os version load commands · 074af2da
  Alexander Shaposhnikov authored Oct 24, 2019
  074af2da
- [AMDGPU] Fold AGPR reg_sequence initializers · d4303b38
  Stanislav Mekhanoshin authored Oct 24, 2019
  d4303b38
- [AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required) · c9c18e5a
  vpykhtin authored Oct 25, 2019
  c9c18e5a
- [DAGCombiner] widen zext of popcount based on target support · e6c145e0
  Sanjay Patel authored Oct 25, 2019
  e6c145e0
- AMDGPU/GlobalISel: Legalize FDIV16 · c35b358b
  Austin Kerbow authored Oct 22, 2019
  c35b358b
- [PowerPC] add test for popcnt with any_extend; NFC · b74d7e5c
  Sanjay Patel authored Oct 25, 2019
  b74d7e5c
- Add an instruction marker field to the ExtraInfo in MachineInstrs. · b85b4e5a
  Amy Huang authored Oct 16, 2019
  b85b4e5a