Commits · d35d8da7d6ac6c08578ec0569b072292631691e0 · Roger Ferrer / llvm-epi · GitLab

Mar 29, 2021
- [AMDGPU] Mark additional VOP3 as commutable · d35d8da7
  Joe Nash authored Mar 23, 2021
  d35d8da7
- [AArch64] Add a few more vector extension tests. · a50037aa
  Florian Hahn authored Mar 29, 2021
  
  a50037aa
- [PrologEpilogInserter][AMDGPU] Only adjust offset for emergency spill slots if the stack grows down · 489ca73a
  Roger Ferrer authored Mar 29, 2021
  489ca73a
- [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register. · 3dd4aa7d
  Craig Topper authored Mar 29, 2021
  3dd4aa7d
- [X86] Always use rip-relative addressing on 64-bit when rematerializing all... · 54bacaf3
  Craig Topper authored Mar 29, 2021
  54bacaf3
- [RISCV] Fix offset computation for RVV · ef76a333
  Roger Ferrer authored Mar 18, 2021
  ef76a333
- [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers · 3abd0bac
  Roger Ferrer authored Mar 18, 2021
  3abd0bac
- [NFC][RISCV] Pass file through update_llc_tests to fix whitespace issues · 96d14ff5
  Roger Ferrer authored Mar 17, 2021
  96d14ff5
- [CSSPGO][llvm-profgen] Context-sensitive global pre-inliner · 30b02323
  Wenlei He authored Mar 05, 2021
  30b02323
- [SampleFDO] Do not scale the magic number NOMORE_ICP_MAGICNUM in value profile · 3cbf4419
  Wei Mi authored Mar 25, 2021
  3cbf4419
- Recommit "[LV] Move runtime pointer size check to LVP::plan()." · c773d0f9
  Florian Hahn authored Mar 29, 2021
  c773d0f9
- [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps · 9745dce8
  Bradley Smith authored Mar 18, 2021
  9745dce8
- Revert "[LV] Move runtime pointer size check to LVP::plan()." · 485c8ce7
  Florian Hahn authored Mar 29, 2021
  485c8ce7
- [SLP] allow matching integer min/max intrinsics as reduction ops · da381cf7
  Sanjay Patel authored Mar 29, 2021
  da381cf7
- [TableGen] Add support for the 'assert' statement in class definitions. · 5f473a04
  Paul C. Anagnostopoulos authored Mar 22, 2021
  5f473a04
- [LV] Move runtime pointer size check to LVP::plan(). · 25fbe803
  Florian Hahn authored Mar 29, 2021
  25fbe803
- [SimpleLoopUnswitch] Fix wrong assertions in partial-unswitch.ll · ab728717
  Jingu Kang authored Mar 29, 2021
  
  ab728717
- Reapply "OpaquePtr: Turn inalloca into a type attribute" · 9a0c9402
  Matt Arsenault authored Mar 29, 2021
  9a0c9402
- [LoopUnswitch] Use reference variables instead of pointer one · e4abb641
  Jingu Kang authored Mar 29, 2021
  e4abb641
- [SimpleLoopUnswitch] Add tests to check partially invariant unswitch · 07142b30
  Jingu Kang authored Mar 29, 2021
  07142b30
- Don't use $ as suffix for symbol names in ThinLTOBitcodeWriter and other places · c6e5c465
  Hans Wennborg authored Feb 25, 2021
  c6e5c465
- Revert "Reapply "OpaquePtr: Turn inalloca into a type attribute"" · 07e46367
  Oliver Stannard authored Mar 29, 2021
  07e46367
- [X86][F16C] Add F16C -O0 test coverage · b5da813f
  Simon Pilgrim authored Mar 29, 2021
  b5da813f
- [X86] Regenerate tests to add missing @PLT · 4e087989
  Simon Pilgrim authored Mar 29, 2021
  
  4e087989
- [X86][SSE] combineHorizOpWithShuffle - consistently use getTargetShuffleInputs to decode shuffles · 805148ea
  Simon Pilgrim authored Mar 28, 2021
  805148ea
- [SVE][Analysis]Instruction costs for ops on scalable-vec · 19601a4c
  Nashe Mncube authored Mar 17, 2021
  19601a4c
- [Orc][tests] Moving one MCJIT test over to Orc to make sure the PowerPC fix worked · 66a8247e
  Stefan Gränitz authored Mar 29, 2021
  66a8247e
- [NFC][LoopUnswitch] Move hasPartialIVCondition to LoopUtils · cfe87d4e
  Jingu Kang authored Mar 29, 2021
  cfe87d4e
- [AMDGPU] Extend gfx10 test coverage. NFC. · b082e6f8
  Petar Avramovic authored Mar 29, 2021
  b082e6f8
- [ARM] Extend MVE lane interleaving to handle other non-instruction leaves · 3a68c6d2
  David Green authored Mar 29, 2021
  3a68c6d2
- [ORC][C-bindings] Fix some ORC C bindings function names and signatures. · 666df2e2
  Lang Hames authored Mar 28, 2021
  666df2e2
- [RISCV] Add a RV64 mulhsu test case. NFC · 5a79909a
  Craig Topper authored Mar 28, 2021
  
  5a79909a
- [ARM] Fix the Changed value in the MVE lane interleaving pass. · 6c88ffed
  David Green authored Mar 28, 2021
  
  6c88ffed
Mar 28, 2021
- [BasicAA] Make sure types match in constant offset heuristic · ce066da8
  Nikita Popov authored Mar 28, 2021
  ce066da8
- [X86] Add phase ordering test for the problem D99427 is trying to solve. NFC · 36b5d09b
  Craig Topper authored Mar 28, 2021
  
  36b5d09b
- [X86] Optimize vXi8 MULHS on targets where we can't sign_extend to the next register size. · 69bdf35d
  Craig Topper authored Mar 28, 2021
  69bdf35d
- [X86][update_llc_test_checks] Use a less greedy regular expression for... · 0248e240
  Craig Topper authored Mar 28, 2021
  0248e240
- [gn build] Port 7b6f760f · 1e9746d2
  LLVM GN Syncbot authored Mar 28, 2021
  
  1e9746d2
- [ARM] MVE vector lane interleaving · 7b6f760f
  David Green authored Mar 28, 2021
  7b6f760f
- [RISCV] Add test case for mulhsu. · 7b35932b
  Craig Topper authored Mar 27, 2021
  7b35932b