Commits · d3df940169a1d2b3b48a62cc422bffa52388a28f · Roger Ferrer / llvm-epi · GitLab

Jan 01, 2012
- Revert 147399. It broke CodeGen/ARM/vext.ll. · d3df9401
  Rafael Espindola authored Jan 01, 2012
  d3df9401
- Fixed a bug in SelectionDAG.cpp. · 67f80c34
  Elena Demikhovsky authored Jan 01, 2012
  67f80c34
- Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. · d51092d9
  Craig Topper authored Dec 31, 2011
  d51092d9
- Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a... · 0e796fee
  Craig Topper authored Dec 31, 2011
  0e796fee
Dec 30, 2011
- Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to... · 6c08930c
  Craig Topper authored Dec 30, 2011
  6c08930c
- Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size,... · 2ca79b9d
  Craig Topper authored Dec 30, 2011
  2ca79b9d
- Cleanup stack/frame register define/kill states. This fixes two bugs: · 692d1fb3
  Hal Finkel authored Dec 30, 2011
  692d1fb3
Dec 28, 2011
- Fix type-checking for load transformation which is not legal on floating-point types. PR11674. · 3a01ddb7
  Eli Friedman authored Dec 28, 2011
  3a01ddb7
- PR11662. · 3c3dd6e5
  Nadav Rotem authored Dec 28, 2011
  3c3dd6e5
- Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. · b3515a8d
  Elena Demikhovsky authored Dec 28, 2011
  b3515a8d
Dec 26, 2011
- Make sure DAGCombiner doesn't introduce multiple loads from the same memory... · e96286cd
  Eli Friedman authored Dec 26, 2011
  e96286cd
Dec 24, 2011
- Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the · a3d54fe0
  Chandler Carruth authored Dec 24, 2011
  a3d54fe0
- Add systematic testing for cttz as well, and fix the bug I spotted by · 38ce2445
  Chandler Carruth authored Dec 24, 2011
  38ce2445
- Add i8 and i64 testing for ctlz on x86. Also simplify the i16 test. · 103ca80f
  Chandler Carruth authored Dec 24, 2011
  103ca80f
- Tidy up this rather crufty test. Put the declarations at the top to make · 44cf0722
  Chandler Carruth authored Dec 24, 2011
  44cf0722
- Expand more when we have a nice 'tzcnt' instruction, to avoid generating · c9fcde23
  Chandler Carruth authored Dec 24, 2011
  c9fcde23
- Tidy up some of these tests. · eeb3a1ce
  Chandler Carruth authored Dec 24, 2011
  eeb3a1ce
- Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the · 7e9453e9
  Chandler Carruth authored Dec 24, 2011
  7e9453e9
- Cleanup this test a bit, sorting things and grouping them more clearly. · 15075d4b
  Chandler Carruth authored Dec 24, 2011
  15075d4b
- Test case for r147232. · 79329ce4
  Akira Hatanaka authored Dec 24, 2011
  79329ce4
Dec 23, 2011
- Experimental support for aligned NEON spills. · 0965585c
  Jakob Stoklund Olesen authored Dec 23, 2011
  0965585c
Dec 21, 2011
- Fix a couple of copy-n-paste bugs. Noticed by George Russell! · 7248bda5
  Chad Rosier authored Dec 21, 2011
  7248bda5
- Fix a couple of copy-n-paste bugs. Noticed by George Russell. · dc8a1aae
  Evan Cheng authored Dec 21, 2011
  dc8a1aae
- Fix bug in zero-store peephole pattern reported in pr11615. · 964c891e
  Akira Hatanaka authored Dec 21, 2011
  964c891e
- Expand 64-bit CTLZ nodes if target architecture does not support it. Add test · 1d8efaba
  Akira Hatanaka authored Dec 21, 2011
  1d8efaba
- Test case for r147017. · bd95275f
  Akira Hatanaka authored Dec 20, 2011
  bd95275f
- Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates · cb2a85bc
  Akira Hatanaka authored Dec 20, 2011
  cb2a85bc
Dec 20, 2011
- 64-bit data directive. · cf10f088
  Akira Hatanaka authored Dec 20, 2011
  cf10f088
- 32-to-64-bit sext_inreg pattern. · 494fdf14
  Akira Hatanaka authored Dec 20, 2011
  494fdf14
- Add code in MipsDAGToDAGISel for selecting constant +0.0. · dac1d48d
  Akira Hatanaka authored Dec 20, 2011
  dac1d48d
- Heed spill slot alignment on ARM. · b95c102c
  Jakob Stoklund Olesen authored Dec 20, 2011
  b95c102c
- ARM target code clean up. Check for iOS, not Darwin where it makes sense. · 68132d80
  Evan Cheng authored Dec 20, 2011
  68132d80
- This is the second fix related to VZEXT_MOVL node. · ec7e6e09
  Elena Demikhovsky authored Dec 20, 2011
  ec7e6e09
- Begin teaching the X86 target how to efficiently codegen patterns that · 24680c24
  Chandler Carruth authored Dec 20, 2011
  24680c24
- Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. · 75f12cc3
  Bob Wilson authored Dec 20, 2011
  75f12cc3
- Move tests to FileCheck. · 3bfaefe9
  Evan Cheng authored Dec 19, 2011
  3bfaefe9
Dec 19, 2011
- Add a test case for r146900. · 37c45db1
  Akira Hatanaka authored Dec 19, 2011
  37c45db1
- Add patterns for matching immediates whose lower 16-bit is cleared. These · db47e0c4
  Akira Hatanaka authored Dec 19, 2011
  db47e0c4
- Remove definitions of double word shift plus 32 instructions. Assembler or · 2a232d81
  Akira Hatanaka authored Dec 19, 2011
  2a232d81
- Remove the restriction on the first operand of the add node in SelectAddr. · 3c9f3363
  Akira Hatanaka authored Dec 19, 2011
  3c9f3363