Commits · d42e09d91ef087b535590e52be88f4b1308acf14 · Roger Ferrer / llvm-epi · GitLab

Mar 26, 2010
- switch the flag for using NEON for SP floating point to a subtarget 'feature'. · 71fcb4fe
  Jim Grosbach authored Mar 25, 2010
  71fcb4fe
- need to fix 'make check' tests first. revert for a moment. · 42bb89c7
  Jim Grosbach authored Mar 25, 2010
  42bb89c7
- switch the flag for using NEON for SP floating point to a subtarget 'feature' · 7fce4e39
  Jim Grosbach authored Mar 25, 2010
  7fce4e39
- Removed instruction class NI from ARMInstrFormats.td. · a3617ec8
  Johnny Chen authored Mar 25, 2010
  a3617ec8
- switch the use-vml[as] instructions flag to a subtarget 'feature' · a43386ba
  Jim Grosbach authored Mar 25, 2010
  a43386ba
Mar 25, 2010
- Add NVDupLnFrm and change NVDupLane class to use that format. · 91d27744
  Johnny Chen authored Mar 25, 2010
  91d27744
- ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu · 4b3b2ef6
  Jim Grosbach authored Mar 25, 2010
  4b3b2ef6
- Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to · d82f9002
  Johnny Chen authored Mar 25, 2010
  d82f9002
- Fix -Asserts warning, again. · d919276b
  Daniel Dunbar authored Mar 25, 2010
  d919276b
- Tag SSE2 integer instructions as SSEPackedInt. · 3758ff91
  Jakob Stoklund Olesen authored Mar 25, 2010
  3758ff91
- Teach TableGen to understand X.Y notation in the TSFlagsFields strings. · f8d7eda6
  Jakob Stoklund Olesen authored Mar 25, 2010
  f8d7eda6
- Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. · 49e121d5
  Jakob Stoklund Olesen authored Mar 25, 2010
  49e121d5
- Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ, · 45ab3f3c
  Johnny Chen authored Mar 25, 2010
  45ab3f3c
- Reapply Kevin's change 94440, now that Chris has fixed the limitation on · e543e7fc
  Bob Wilson authored Mar 25, 2010
  e543e7fc
- eliminate a bunch more parallels now that scheduling · 23bf99a9
  Chris Lattner authored Mar 25, 2010
  23bf99a9
- Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this: · b07a29ec
  Evan Cheng authored Mar 25, 2010
  b07a29ec
- Speculatively revert this to see if it fixes buildbot failures. · 5b2da69f
  Bob Wilson authored Mar 24, 2010
  5b2da69f
Mar 24, 2010
- Added the Advanced Encryption Standard (AES) Instructions. · f5584a73
  Kevin Enderby authored Mar 24, 2010
  f5584a73
- Make the use of the vmla and vmls VFP instructions controllable via cmd line. · 34de7768
  Jim Grosbach authored Mar 24, 2010
  34de7768
- Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does · b96eb684
  Kevin Enderby authored Mar 24, 2010
  b96eb684
- Per chris's request, add some comments. · 2ceb2884
  Nate Begeman authored Mar 24, 2010
  2ceb2884
- Trivial formating change. · bff23ca6
  Johnny Chen authored Mar 24, 2010
  bff23ca6
- BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts. · 583e05d8
  Nate Begeman authored Mar 24, 2010
  583e05d8
- Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. · e99953ce
  Johnny Chen authored Mar 24, 2010
  e99953ce
- Reverted r99376. The disassembler will deal with the 2-reg format of these two · da44d597
  Johnny Chen authored Mar 24, 2010
  da44d597
- tweak the arm if conversion heuristic · 07607382
  Jim Grosbach authored Mar 24, 2010
  07607382
- Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. · aa9b1c81
  Johnny Chen authored Mar 24, 2010
  aa9b1c81
- Switch INC8r to defining its pattern in terms of X86inc_flag · 9096bcde
  Chris Lattner authored Mar 24, 2010
  9096bcde
- Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, · 9b1f60ad
  Johnny Chen authored Mar 24, 2010
  9b1f60ad
- switch SDTBinaryArithWithFlags to be a multiple-result node as well. · f9c8bec6
  Chris Lattner authored Mar 24, 2010
  f9c8bec6
- Switch SDTUnaryArithWithFlags to being modeled as a two-result · db1ac3cf
  Chris Lattner authored Mar 24, 2010
  db1ac3cf
- remove 64-bit or_is_add parallels. · cca83a7a
  Chris Lattner authored Mar 24, 2010
  cca83a7a
- remove useless or_is_add parallel's. · f5e50043
  Chris Lattner authored Mar 24, 2010
  f5e50043
- reduce nesting. · 237d38e7
  Chris Lattner authored Mar 24, 2010
  237d38e7
- try being more permissive for if-conversion on ARM V7. see what the nightly · e0874fa0
  Jim Grosbach authored Mar 24, 2010
  e0874fa0
- Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings." · a86ccbfe
  Jakob Stoklund Olesen authored Mar 23, 2010
  a86ccbfe
- [llvm_void_ty] is no longer needed for result types, · 3d9ec391
  Chris Lattner authored Mar 23, 2010
  3d9ec391
- Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. · 31da45b7
  Jakob Stoklund Olesen authored Mar 23, 2010
  31da45b7
- Renamed NVdImmFrm to N1RegModImmFrm. · 6a64320d
  Johnny Chen authored Mar 23, 2010
  6a64320d
Mar 23, 2010
- Fix typo in the comment for N3VX class. · 8a687233
  Johnny Chen authored Mar 23, 2010
  8a687233