Commits · d4ab74ee0b37c930ce7446caa55f2a8c829197fe · Roger Ferrer / llvm-epi · GitLab

Oct 16, 2019
- [AMDGPU] Supress unused sdwa insts generation · d4ab74ee
  Stanislav Mekhanoshin authored Oct 16, 2019
  d4ab74ee
- [AArch64,Assembler] Compiler support for ID_MMFR5_EL1 · b6dd1286
  Mark Murray authored Oct 16, 2019
  b6dd1286
- bpf: fix wrong truncation elimination when there is back-edge/loop · ec518510
  Jiong Wang authored Oct 16, 2019
  ec518510
- [RISCV] Add MachineInstr immediate verification · 1893f9a4
  Luis Marques authored Oct 16, 2019
  1893f9a4
- [AMDGPU] Fix-up cases where writelane has 2 SGPR operands · 2d6a2303
  David Stuttard authored Oct 16, 2019
  2d6a2303
- [ARM] Add a register class for GPR pairs without SP and use it. NFCI · 95b5d459
  Mikhail Maltsev authored Oct 16, 2019
  95b5d459
- [AMDGPU] Extend the SI Load/Store optimizer · 02baaca7
  Piotr Sobczak authored Oct 16, 2019
  02baaca7
- [ARM][ParallelDSP] Change smlad insertion order · 1c3ca612
  Sam Parker authored Oct 16, 2019
  1c3ca612
Oct 15, 2019
- AMDGPU: Fix infinite searches in SIFixSGPRCopies · 527e9f9a
  Austin Kerbow authored Oct 15, 2019
  527e9f9a
- Added support for "#pragma clang section relro=<name>" · f14642f2
  Dmitry Mikulin authored Oct 15, 2019
  f14642f2
- [WebAssembly] Allow multivalue types in block signature operands · 2cb27072
  Thomas Lively authored Oct 15, 2019
  2cb27072
- [X86] combineX86ShufflesRecursively - split the getTargetShuffleInputs call... · 50dc09dd
  Simon Pilgrim authored Oct 15, 2019
  50dc09dd
- [X86] Make memcmp() use PTEST if possible and also enable AVX1 · 59390efe
  David Zarzycki authored Oct 15, 2019
  59390efe
- [AMDGPU] Support mov dpp with 64 bit operands · 1184c27f
  Stanislav Mekhanoshin authored Oct 15, 2019
  1184c27f
- [AMDGPU] Allow DPP combiner to work with REG_SEQUENCE · 6e8599d9
  Stanislav Mekhanoshin authored Oct 15, 2019
  6e8599d9
- [Alignment][NFC] Value::getPointerAlignment returns MaybeAlign · bae629b9
  Guillaume Chatelet authored Oct 15, 2019
  bae629b9
- [ARM][MVE] validForTailPredication insts · ce39278f
  Sam Parker authored Oct 15, 2019
  ce39278f
- [Alignment] Migrate Attribute::getWith(Stack)Alignment · b65fa483
  Guillaume Chatelet authored Oct 15, 2019
  b65fa483
- [Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned) · 0e62011d
  Guillaume Chatelet authored Oct 15, 2019
  0e62011d
- [X86] Resolve KnownUndef/KnownZero bits into target shuffle masks in helper. NFCI. · 70778444
  Simon Pilgrim authored Oct 15, 2019
  70778444
- [MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store · 599591f3
  Petar Avramovic authored Oct 15, 2019
  599591f3
- [MIPS GlobalISel] Refactor MipsRegisterBankInfo [NFC] · f7c213c9
  Petar Avramovic authored Oct 15, 2019
  f7c213c9
- [X86] Don't check for VBROADCAST_LOAD being a user of the source of a... · b2661a2d
  Craig Topper authored Oct 15, 2019
  b2661a2d
- [RISCV] Support fast calling convention · 078bec6c
  Shiva Chen authored Oct 15, 2019
  078bec6c
- [WebAssembly] Trapping fptoint builtins and intrinsics · 232fd99d
  Thomas Lively authored Oct 15, 2019
  232fd99d
- [X86] Teach X86MCodeEmitter to properly encode zmm16-zmm31 as index register... · 9586d85a
  Craig Topper authored Oct 14, 2019
  9586d85a
- [ARM][AsmParser] handles offset expression in parentheses · e9089c22
  Jian Cai authored Oct 14, 2019
  e9089c22
Oct 14, 2019
- AMDGPU: Fix redundant setting of m0 for atomic load/store · 2bd166ad
  Matt Arsenault authored Oct 14, 2019
  2bd166ad
- [NVPTX] Restructure shfl instrinsics and add variants that return a predicate. · 5c6ab2a0
  Artem Belevich authored Oct 14, 2019
  5c6ab2a0
- [CostModel][X86] Add CTLZ scalar costs · 1385b27e
  Simon Pilgrim authored Oct 14, 2019
  1385b27e
- [ARM] Selection for MVE VMOVN · 54323623
  David Green authored Oct 14, 2019
  54323623
- [CostModel][X86] Add CTPOP scalar costs (PR43656) · 151bbba7
  Simon Pilgrim authored Oct 14, 2019
  151bbba7
- [AArch64] Stackframe accesses to SVE objects. · 77748129
  Sander de Smalen authored Oct 14, 2019
  77748129
- [AMDGPU] Come back patch for the 'Assign register class for cross block values... · c4d256a5
  Alexander Timofeev authored Oct 14, 2019
  c4d256a5
- [X86][BtVer2] Improved latency and throughput of float/vector loads and stores. · b744abb4
  Andrea Di Biagio authored Oct 14, 2019
  b744abb4
- [NFC][TTI] Add Alignment for isLegalMasked[Load/Store] · 527a35e1
  Sam Parker authored Oct 14, 2019
  527a35e1
- [X86] Teach EmitTest to handle ISD::SSUBO/USUBO in order to use the Z flag... · f4d03213
  Craig Topper authored Oct 14, 2019
  f4d03213
Oct 13, 2019
- [X86] getTargetShuffleInputs - Control KnownUndef mask element resolution as well as KnownZero. · 11495e5a
  Simon Pilgrim authored Oct 13, 2019
  11495e5a
- [X86] Enable use of avx512 saturating truncate instructions in more cases. · 25eb2199
  Craig Topper authored Oct 13, 2019
  25eb2199
- [X86] SimplifyMultipleUseDemandedBitsForTargetNode - use... · 3efafd6c
  Simon Pilgrim authored Oct 13, 2019
  3efafd6c