Commits · d4e183f68631019fe51f855a554988292868b9ac · Roger Ferrer / llvm-epi · GitLab

Jun 17, 2020
- Revert "[LV] Emit @llvm.get.active.mask for tail-folded loops" · d4e183f6
  Sjoerd Meijer authored Jun 17, 2020
  d4e183f6
- [LV] Emit @llvm.get.active.mask for tail-folded loops · 47650451
  Sjoerd Meijer authored Jun 10, 2020
  47650451
- [TTI] Refactor emitGetActiveLaneMask · 20835cff
  Sjoerd Meijer authored Jun 09, 2020
  20835cff
- [SystemZ] Bugfix in storeLoadCanUseBlockBinary(). · d3f7448e
  Jonas Paulsson authored Jun 11, 2020
  d3f7448e
- [NFC]][PowerPC] Remove unused intrinsic for old CTR loop pass · c2574dc9
  Kang Zhang authored Jun 17, 2020
  c2574dc9
- AMDGPU/GlobalISel: Fix obvious bug in ported 32-bit udiv/urem · 3b34f3fc
  Matt Arsenault authored Jun 16, 2020
  3b34f3fc
- AMDGPU: Remove intermediate DAG node for trig_preop intrinsic · c5c58fd6
  Matt Arsenault authored Jun 16, 2020
  c5c58fd6
Jun 16, 2020
- [gicombiner] Allow generated combiners to store additional members · e35ba099
  Daniel Sanders authored Jun 16, 2020
  e35ba099
- [SVE] Eliminate calls to default-false VectorType::get() from AArch64 · 616d8d94
  Christopher Tetreault authored Jun 16, 2020
  616d8d94
- [PowerPC] Add -m[no-]power10-vector clang and llvm option · 37e72f47
  Ahsan Saghir authored Jun 16, 2020
  37e72f47
- Fix ubsan error in tblgen with signed left shift · 3f0c9c16
  Stanislav Mekhanoshin authored Jun 16, 2020
  3f0c9c16
- [AArch64][GlobalISel] Avoid creating redundant ubfx when selecting G_ZEXT · 7caa9caa
  Jessica Paquette authored Jun 15, 2020
  7caa9caa
- [AArch64]: BFloat MatMul Intrinsics&CodeGen · 10b6567f
  Luke Geeson authored Jun 09, 2020
  10b6567f
- [AArch64]: BFloat Load/Store Intrinsics&CodeGen · 508a4764
  Luke Geeson authored Jun 09, 2020
  508a4764
- [AVR] Remove faulty stack pushing behavior · 5aa8014c
  Ayke van Laethem authored Apr 21, 2020
  5aa8014c
- [AVR] Fix stack size in functions with a frame pointer · 3ab1c97e
  Ayke van Laethem authored Apr 21, 2020
  3ab1c97e
- [ARM] Fix crash trying to generate i1 immediates · f269bb7d
  David Green authored Jun 16, 2020
  f269bb7d
- Fix comment typo - Uexpected -> Unexpected. NFC. · 9d11822f
  Simon Pilgrim authored Jun 16, 2020
  
  9d11822f
- Silence GCC 7 warning · 503a26d8
  Kristof Beyls authored Jun 16, 2020
  503a26d8
- [ARM][NFC] Explicitly specify the fp16 value type in codegen patterns. · f6189da9
  Alexandros Lamprineas authored Jun 16, 2020
  f6189da9
- [X86][SSE] combineVectorSizedSetCCEquality - remove unused AVX2 MOVMSK path. NFCI. · 379c5b31
  Simon Pilgrim authored Jun 15, 2020
  379c5b31
- [X86][SSE] MatchVectorAllZeroTest - handle OR vector reductions · 057c9c7e
  Simon Pilgrim authored Jun 16, 2020
  057c9c7e
- [X86][SSE] combineVectorSizedSetCCEquality - move single Subtarget.hasAVX()... · 65c3fa84
  Simon Pilgrim authored Jun 15, 2020
  65c3fa84
- [AArch64] Print the immediate operand for SPACE pseudo instruction · a3b5f428
  Fangrui Song authored Jun 15, 2020
  a3b5f428
- [AArch64][GlobalISel] Emit constant pool loads for 64 bit fp immediates. · 1035a416
  Amara Emerson authored Jun 15, 2020
  1035a416
- [X86] Add support for inline assembly 'x' constraint for i128. · 255d5dba
  Craig Topper authored Jun 15, 2020
  255d5dba
- [AMDGPU] make ubsan happy with unsigned left shift · 576fa5a5
  Stanislav Mekhanoshin authored Jun 15, 2020
  576fa5a5
- [AMDGPU] Add gfx1030 target · 9ee272f1
  Stanislav Mekhanoshin authored Jun 15, 2020
  9ee272f1
Jun 15, 2020
- [PPCAsmPrinter] support 'L' output template for memory operands · 2d8e105d
  Nick Desaulniers authored Jun 15, 2020
  2d8e105d
- [AArch64][GlobalISel] Add G_EXT and select ext using it · 3495b884
  Jessica Paquette authored Jun 08, 2020
  3495b884
- [Target/PPC] Fold inside an assertion. · e51e8274
  Davide Italiano authored Jun 15, 2020
  e51e8274
- AMDGPU/GlobalISel: Don't hardcode maximum register size · e07cf923
  Matt Arsenault authored Jun 13, 2020
  e07cf923
- AMDGPU/GlobalISel: Extend load/store workaround to i128 vectors · 1a7f115d
  Matt Arsenault authored Jun 15, 2020
  
  1a7f115d
- [LLVM] Change isa<> to a variadic function template · 72d20b96
  Rahul Joshi authored Jun 15, 2020
  72d20b96
- [Target/PPC] Silence an unused variable warning. NFC. · 5cb44196
  Davide Italiano authored Jun 15, 2020
  
  5cb44196
- Recommit "[X86] Separate imm from relocImm handling." · d72cb4ce
  Craig Topper authored Jun 15, 2020
  d72cb4ce
- [WebAssembly] Adding 64-bit version of R_WASM_MEMORY_ADDR_* relocs · 3b29376e
  Wouter van Oortmerssen authored Jun 05, 2020
  3b29376e
- [X86] Remove printanymem/printopaquemem from the InstPrinters. Just tell... · ad1c46c3
  Craig Topper authored Jun 15, 2020
  ad1c46c3
- [llvm][SVE] IR intrinsics for quadword permutation instructions. · 28a00ac9
  Francesco Petrogalli authored Jun 15, 2020
  28a00ac9
- AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads · 2ca55232
  Matt Arsenault authored May 30, 2020
  2ca55232