Commits · d5be48c66d3e5e8be21805c3a33dc67a20e258be · Roger Ferrer / llvm-epi · GitLab

Jan 12, 2022
- [X86][AVX2] Add SimplifyDemandedVectorElts handling for avx2 per element shifts · de3808c8
  Simon Pilgrim authored Jan 12, 2022
  de3808c8
- [X86][AVX2] Add tests for missing demanded elts handling for avx2 per element shifts · 0c8d30a3
  Simon Pilgrim authored Jan 12, 2022
  0c8d30a3
- [NFC] Run script to autogenerate CHECK lines for CodeGen/AArch64/fast-isel-cmp-vec.ll · b5493ff5
  David Sherwood authored Jan 12, 2022
  
  b5493ff5
- [X86][XOP] Add SimplifyDemandedVectorElts handling for xop shifts · c2426fdc
  Simon Pilgrim authored Jan 12, 2022
  c2426fdc
- [X86][XOP] Add tests for missing demanded elts handling for xop shifts · 13362abf
  Simon Pilgrim authored Jan 12, 2022
  13362abf
- [X86][MS] Change the alignment of f80 to 16 bytes on Windows 32bits to match with ICC · 1bb0caf5
  Phoebe Wang authored Dec 17, 2021
  1bb0caf5
- [ARM] Remove FeaturePerfMon from armv7-m · 351edf1c
  David Green authored Jan 12, 2022
  351edf1c
- [X86][ABI] Pre-commit test for the f80 ABI alignment change. NFC · 95a436f8
  Phoebe Wang authored Dec 17, 2021
  
  95a436f8
- [DAGCombiner][AArch64] precommit some tests for D116915 NFC · dc01fb1d
  zhongyunde authored Jan 12, 2022
  dc01fb1d
- [AMDGPU] Do not reserve any VGPR for SGPR spills · 8470bf2b
  Austin Kerbow authored Jan 11, 2022
  8470bf2b
- [RISCV] Add strictfp support for compares. · 63b17eb9
  Craig Topper authored Jan 11, 2022
  63b17eb9
Jan 11, 2022
- Revert D109159 : Revert "[amdgpu] Enable selection of `s_cselect_b64`." · c0581f7d
  David Salinas authored Jan 05, 2022
  c0581f7d
- AMDGPU/GlobalISel: Regenerate baseline checks to include -NEXT · 0cf860ec
  Matt Arsenault authored Jan 11, 2022
  
  0cf860ec
- [llvm][test] rewrite callbr to use i rather than X constraint NFC · 79ebc3b0
  Nick Desaulniers authored Jan 11, 2022
  79ebc3b0
- [SelectionDAG] treat X constrained labels as i for asm · 4edb9983
  Nick Desaulniers authored Jan 11, 2022
  4edb9983
- [ShrinkWrap] check for PPC's non-callee-saved LR · 9c4b49db
  Nick Desaulniers authored Jan 11, 2022
  9c4b49db
- X86InstrInfo: Support immediates that are +1/-1 different in optimizeCompareInstr · ad25f8a5
  Matthias Braun authored Sep 27, 2021
  ad25f8a5
- [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn) · be1cc64c
  Craig Topper authored Jan 11, 2022
  be1cc64c
- [X86] Tag existing shuffle test case as PR53124 · 4eda7be1
  Simon Pilgrim authored Jan 11, 2022
  4eda7be1
- [SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE · 3a272d1e
  David Sherwood authored Dec 16, 2021
  3a272d1e
- ARM: make FastISel & GISel pass -1 to ADJCALLSTACKUP to signal no callee pop. · 0b5b35fd
  Tim Northover authored Jan 07, 2022
  0b5b35fd
- [RISCV] Generate 32 bits jumptable entries when code model is small · c6430fad
  Pengcheng Wang authored Jan 11, 2022
  c6430fad
- [IR] Change vector.splice intrinsic to reject out-of-bounds indices · 51497dc0
  David Sherwood authored Dec 17, 2021
  51497dc0
- [CSKY] Add CSKYConstantIslands Pass to lift or duplicate constant pool entry · 065e0324
  Zi Xuan Wu authored Jan 11, 2022
  065e0324
- [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT · 98d51c25
  Pengcheng Wang authored Jan 11, 2022
  98d51c25
- [RISCV] Block vmsgeu.vi with 0 immediate in Isel · 9ea772ff
  Chenbing.Zheng authored Jan 11, 2022
  9ea772ff
- [RISCV] Select vl op to X0 when it is equal to ~0. · d0554ae4
  Jianjian GUAN authored Jan 07, 2022
  d0554ae4
- [RISCV] Add precommit test for select vl op that equal to ~0. · 99c1acf3
  Jianjian GUAN authored Jan 07, 2022
  99c1acf3
- [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled · bd653f64
  Haocong.Lu authored Jan 11, 2022
  bd653f64
- [RISCV] Use vmv.s.x to build one element splat vector. · b607cd39
  Jianjian GUAN authored Dec 25, 2021
  b607cd39
Jan 10, 2022
- Fix a missed opportunity to merge stores. · e2cc091a
  Nadav Rotem authored Jan 10, 2022
  e2cc091a
- AMDGPU/GlobalISel: Explicitly track d16 for image legalization · 8e682086
  Matt Arsenault authored Jan 09, 2022
  8e682086
- GlobalISel: Pass DebugLoc to getFunctionLiveInPhysReg · 0ba4e4b5
  Matt Arsenault authored Jan 09, 2022
  0ba4e4b5
- AMDGPU: Avoid null check during addrspacecast lowering · 68468bbe
  Matt Arsenault authored Dec 28, 2021
  68468bbe
- [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC · b271184f
  Craig Topper authored Jan 10, 2022
  b271184f
- [Thumb2] Regenerate test checks (NFC) · 75433654
  Nikita Popov authored Jan 10, 2022
  
  75433654
- AArch64: don't claim to preserve registers used by prologue code · 581e8556
  Tim Northover authored Nov 16, 2021
  
  581e8556
- [AArch64][SVE] Fold predicate into compare · eee993ae
  Cullen Rhodes authored Jan 10, 2022
  eee993ae
- [NFC] Add tests for splats of illegal integer vector types · 8e773f44
  David Sherwood authored Jan 07, 2022
  8e773f44
- [RISCV] Generalize (srl (and X, 0xffff), C) -> (srli (slli X, (XLen-16),... · b645bcd9
  Craig Topper authored Jan 09, 2022
  b645bcd9