Commits · d60ae47f9dabcbc42b894f988b51d4643447b599 · Roger Ferrer / llvm-epi · GitLab

May 20, 2022
- [RISCV] Fix logic for determining RVV stack padding · d60ae47f
  Fraser Cormack authored May 19, 2022
  d60ae47f
- [RISCV] Add a test showing overlapping stack offsets with RVV · a3510707
  Fraser Cormack authored May 19, 2022
  a3510707
- Minutes for pauth sync-ups have moved to Discourse. · 52f2d057
  Kristof Beyls authored May 20, 2022
  
  52f2d057
- [AMDGPU] Add a test case for an SIFoldOperands bug · a71a4485
  Jay Foad authored May 20, 2022
  
  a71a4485
- tsan: add lock free stack pattern test · 5deca650
  Alexey Katranov authored May 20, 2022
  5deca650
- [X86][AMX][NFC] Refactor X86LowerAMXCast.cpp · d5999bd3
  Luo, Yuanke authored May 20, 2022
  d5999bd3
- [AMDGPU][MC][GFX8+] Correct SMEM offset parsing · f598dfb3
  Dmitry Preobrazhensky authored May 20, 2022
  f598dfb3
- [mlir] do not elide dialect prefix for ops with dots in the name · 122e6858
  Alex Zinenko authored May 19, 2022
  122e6858
- [ARM] Cost modelling for MVE vector fptoi_sat · b4dd9fc3
  David Green authored May 20, 2022
  b4dd9fc3
- [AArch64][SME]Tied up ZA operand for accumulate instructions · 4cd95104
  Caroline Concatto authored May 12, 2022
  4cd95104
- [AArch64][SME][NFC] Add implicit operands for SME instructions in the disassembly. · 8765ad42
  Caroline Concatto authored May 13, 2022
  8765ad42
- [flang] Fix use-associated false-positive error · a61835b1
  Daniil Dudkin authored May 20, 2022
  a61835b1
- [LV] Do not LoopSimplify/LCSSA after generating main vector loop. · cd61d4bd
  Florian Hahn authored May 20, 2022
  cd61d4bd
- [NFC][test] Fix the line num of expected-error for CSKY at builtin-alloca-with-align.c · 632cfbc9
  Zi Xuan Wu authored May 20, 2022
  
  632cfbc9
- [AArch64] Fix the generation of BE Nops · 1379b150
  David Green authored May 20, 2022
  1379b150
- [amdgpu] Add amdgpu_kernel calling conv attribute to clang · 83c431fb
  Jon Chesterfield authored May 20, 2022
  83c431fb
- Make CompoundStmtBitfields::NumStmts not a bit-field · 5537b22c
  Serge Pavlov authored May 15, 2022
  5537b22c
- [flang][OpenMP] Fix the types of worksharing-loop variables · 870f4421
  Peixin-Qiao authored May 20, 2022
  870f4421
- [RISCV] Add VL patterns for vector widening floating-point fused multiply-add instructions. · 8fc4fcec
  Jianjian GUAN authored Apr 27, 2022
  8fc4fcec
- [RISCV][NFC] Remove `*=` operator for LMULType · da201aa4
  eopXD authored May 19, 2022
  da201aa4
- [MIR] Provide location of extra instruction operand when diagnosing it. · 86803008
  Ivan Kosarev authored May 20, 2022
  86803008
- [lldb] Update test_software_breakpoint_set_and_remove_work for AS · b9a30b69
  Jonas Devlieghere authored May 19, 2022
  b9a30b69
- [lldb] Fix 'ptsname_r' is only available on macOS 10.13.4 or newer · ea486400
  Jonas Devlieghere authored May 19, 2022
  ea486400
- [RISCV] Add test showing codegen for unaligned loads and stores of scalar types · 3e5b1e9c
  Philip Reames authored May 19, 2022
  
  3e5b1e9c
- [ASan] Add sleep_before_init flag · ec563c5a
  Julian Lettner authored May 19, 2022
  ec563c5a
- [InstCombine] [NFC] Use a pattern matcher for ExtractElementInst · cf348f6a
  Chenbing Zheng authored May 20, 2022
  cf348f6a
- [lit] Fix setup of sanitizer environment · d33c3623
  Vitaly Buka authored May 19, 2022
  d33c3623
- [mlir][Arithmetic] fold overlapping negf. · 0e02bf63
  Jianjian GUAN authored May 19, 2022
  0e02bf63
- [AArch64] Add support for -fzero-call-used-regs · 6e00a34c
  Bill Wendling authored May 19, 2022
  6e00a34c
- [mlir][sparse] Adding x-macros for OverheadType · a9a19f59
  wren romano authored May 19, 2022
  a9a19f59
- [Serialization] Delta encode locations in expansion sloc entries · 1dfd8e99
  Sam McCall authored May 19, 2022
  1dfd8e99
- [bazel][libc] Fix bazel build · c3856cb7
  Alex Brachet authored May 19, 2022
  c3856cb7
- [mlir][sparse] Factored out a "FATAL" macro for unrecoverable assertion failure · 774674ce
  wren romano authored May 19, 2022
  774674ce
- [TableGen] Add generation of argument register lists · 88043c19
  Bill Wendling authored May 19, 2022
  88043c19
- Revert "[TableGen] Add generation of argument register lists" · db0ea51c
  Bill Wendling authored May 19, 2022
  db0ea51c
- [mlir][sparse] Simplifying closure · aff9c89f
  wren romano authored May 19, 2022
  aff9c89f
- [mlir][sparse] Using the name "dimSizes" more consistently · fa6aed2a
  wren romano authored May 19, 2022
  fa6aed2a
- [TableGen] Add generation of argument register lists · 3fa1b655
  Bill Wendling authored May 19, 2022
  3fa1b655
May 19, 2022
- [DirectX backend] When cleanup module flags only remove unused flags. · c6c13d4e
  python3kgae authored May 17, 2022
  c6c13d4e
- [libc] Add strlcat · b1183305
  Alex Brachet authored May 19, 2022
  b1183305