Commits · d6144c30fb6ae7ac15c82d512f8da7572577c2d2 · Roger Ferrer / llvm-epi · GitLab

Jun 26, 2021
- [ARM] Introduce MVETRUNC ISel lowering · 59558129
  David Green authored Jun 26, 2021
  59558129
- [RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions. · 81b2f959
  Craig Topper authored Jun 26, 2021
  
  81b2f959
- [ARM] MVE vabd · 0f83d37a
  David Green authored Jun 26, 2021
  0f83d37a
- [ISel] Port AArch64 SABD and UABD to DAGCombine · 2887f146
  David Green authored Jun 26, 2021
  2887f146
- [RISCV][NFC] Combine the control flow for different RetOp of interrupt function · 779d2b0a
  Jim Lin authored Jun 26, 2021
  779d2b0a
- [RISCV] Add DAG combine to detect opportunities to replace (i64 (any_extend... · d4f4a1ba
  Craig Topper authored Jun 25, 2021
  d4f4a1ba
- [ms] [llvm-ml] Disable C-style comments · e074d580
  Eric Astor authored Jun 25, 2021
  
  e074d580
- [X86] Selecting fld0 for undefined value in fast ISEL. · 36003c20
  Luo, Yuanke authored Jun 22, 2021
  36003c20
- Disable ReplaceLDS pass, patch up tests to match · 50ad3478
  Jon Chesterfield authored Jun 26, 2021
  50ad3478
Jun 25, 2021
- [PowerPC] Disable combine 64-bit bswap(load) without LDBRX · 4e22c726
  Nemanja Ivanovic authored Jun 25, 2021
  4e22c726
- [SystemZ] Add support for .reloc assembler directive · b2674670
  Ulrich Weigand authored Jun 25, 2021
  b2674670
- [X86] Simplify part of the isel for X86ISD::FCMP/STRICT_FCMP/STRICT_FCMPS. · 0f3bc00a
  Craig Topper authored Jun 25, 2021
  0f3bc00a
- Revert "[GlobalISel] NFC: Have LLT::getSizeInBits/Bytes return a TypeSize." · b732e6c9
  Sander de Smalen authored Jun 25, 2021
  b732e6c9
- [GlobalISel] NFC: Have LLT::getSizeInBits/Bytes return a TypeSize. · aeab9d95
  Sander de Smalen authored Jun 25, 2021
  aeab9d95
- [AMDGPU] Removed unused Predicate HasOffset3fBug. NFC. · c3cc9d1e
  Jay Foad authored Jun 25, 2021
  c3cc9d1e
- [Hexagon] Convert getTypeAlignment to return Align · 8a9ec39b
  Krzysztof Parzyszek authored Jun 25, 2021
  8a9ec39b
- [GlobalISel] NFC: Change LLT::changeNumElements to LLT::changeElementCount. · c9acd2f3
  Sander de Smalen authored Jun 25, 2021
  c9acd2f3
- [GlobalISel] NFC: Change LLT::scalarOrVector to take ElementCount. · 968980ef
  Sander de Smalen authored Jun 25, 2021
  968980ef
- [AArch64] Custom lower <4 x i8> loads · 51e434fc
  Sjoerd Meijer authored Jun 24, 2021
  51e434fc
- [PowerPC] Change VSRpRC allocation order · a08fc136
  Qiu Chaofan authored Jun 25, 2021
  a08fc136
- [ARM] Fix crash in chained BFI combine due to incorrectly RAUW'ing a node. · f9b3840c
  Amara Emerson authored Jun 24, 2021
  f9b3840c
- [RISCV] Permit larger RVV stacks and stack offsets · ab1bd255
  Fraser Cormack authored Jun 22, 2021
  ab1bd255
- [X86] Add description of FXAM instruction · b36d214b
  Serge Pavlov authored Jun 23, 2021
  b36d214b
- [PowerPC] Move PPCBranchSelector as close to asm printer as possible · b904574b
  Kai Luo authored Jun 25, 2021
  b904574b
- [PowerPC] Fix bswap combine for big endian systems · dcccb2f5
  Nemanja Ivanovic authored Jun 24, 2021
  dcccb2f5
Jun 24, 2021
- [llvm] Rename StringRef _lower() method calls to _insensitive() · 42f74e82
  Martin Storsjö authored Jun 23, 2021
  42f74e82
- [Hexagon] Opaquify pointer usage in GEP commoning · d09218a8
  Krzysztof Parzyszek authored Jun 24, 2021
  
  d09218a8
- [PowerPC] Combine 64-bit bswap(load) without LDBRX · 0464586a
  Nemanja Ivanovic authored Jun 24, 2021
  0464586a
- [AMDGPU] Add gfx1035 target · 3453f3dd
  Aakanksha Patil authored Jun 24, 2021
  3453f3dd
- [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) · 571c8c52
  Pablo Barrio authored Jun 15, 2021
  571c8c52
- [AsmParser][SystemZ][z/OS] Support for emitting labels in upper case · 63136266
  Anirudh Prasad authored Jun 24, 2021
  63136266
- [ARM] Extend narrow values to allow using truncating scatters · 1113e068
  David Green authored Jun 24, 2021
  1113e068
- [X86] Exclude invalid element types for bitcast/broadcast folding. · a54c6fc0
  Florian Hahn authored Jun 24, 2021
  a54c6fc0
- [CostModel][AArch64] Improve cost model for vector reduction intrinsics · 0c4651f0
  Rosie Sumpter authored Jun 15, 2021
  0c4651f0
- [X86] Fold nested select_cc to select (cmp*ge/le Cond0, Cond1), LHS, Y) · c4d3eedc
  Simon Pilgrim authored Jun 24, 2021
  c4d3eedc
- [GlobalISel] NFC: Change LLT::vector to take ElementCount. · d5e14ba8
  Sander de Smalen authored Jun 24, 2021
  d5e14ba8
- [RISCV] Lower RVV vector SELECTs to VSELECTs · a4729f7f
  Fraser Cormack authored Jun 23, 2021
  a4729f7f
- [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs · 98f48723
  Carl Ritson authored Jun 24, 2021
  98f48723
- Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken... · 660cae84
  Jon Chesterfield authored Jun 24, 2021
  660cae84
Jun 23, 2021
- [AMDGPU] Check for pointer operand while refining LDS align · d274d64e
  Stanislav Mekhanoshin authored Jun 23, 2021
  d274d64e