Commits · d6317d22a92d596731b1dd9d4a8010879f3e43d9 · Roger Ferrer / llvm-epi · GitLab

Jan 19, 2019
- [X86] Deduplicate static calling convention helpers for code size, NFC · 38f9900a
  Reid Kleckner authored Jan 19, 2019
  38f9900a
Jan 18, 2019
- AMDGPU/GlobalISel: Legalize more types for select · 96e47014
  Matt Arsenault authored Jan 18, 2019
  96e47014
- AMDGPU/GlobalISel: Legalize illegal g_constant · 4599159a
  Matt Arsenault authored Jan 18, 2019
  4599159a
- AMDGPU: Remove llvm.SI.load.const · 85af701e
  Matt Arsenault authored Jan 18, 2019
  85af701e
- [X86] Lower avx512f scatter intrinsics to X86MaskedScatterSDNode instead of... · 08d3d32e
  Craig Topper authored Jan 18, 2019
  08d3d32e
- [X86] Lower avx2/avx512f gather intrinsics to X86MaskedGatherSDNode instead of... · b9d4461f
  Craig Topper authored Jan 18, 2019
  b9d4461f
- [AMDGPU] Add some missing always-uniform values. · 3ed09f8e
  Neil Henning authored Jan 18, 2019
  3ed09f8e
- [x86] simplify code for SDValue.getOperand(); NFC · b6c91a1a
  Sanjay Patel authored Jan 18, 2019
  b6c91a1a
- [AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands · 6bc26aaa
  Dmitry Preobrazhensky authored Jan 18, 2019
  6bc26aaa
- [AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructions · 61105bab
  Dmitry Preobrazhensky authored Jan 18, 2019
  61105bab
- [AVR] Fix codegen bug in 16-bit loads · 77364be4
  Dylan McKay authored Jan 18, 2019
  77364be4
- [AVR] Rewrite the CBRRdK instruction as an alias of ANDIRdK · d770da98
  Dylan McKay authored Jan 18, 2019
  d770da98
- [AVR] Expand 8/16-bit multiplication to libcalls on MCUs that don't have hardware MUL · 7203e00b
  Dylan McKay authored Jan 18, 2019
  7203e00b
- [WebAssembly] Add languages from debug info to producers section · c6795e07
  Thomas Lively authored Jan 18, 2019
  c6795e07
Jan 17, 2019
- [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25 · 3daf8bc9
  Vladimir Stefanovic authored Jan 17, 2019
  3daf8bc9
- Fix the buildbot failure introduced by r351404 · 4d145029
  Sanjin Sijaric authored Jan 17, 2019
  4d145029
- [WebAssembly] Fixed objdump not parsing function headers. · f3b762a0
  Wouter van Oortmerssen authored Jan 17, 2019
  f3b762a0
- Allow FP types for atomicrmw xchg · 0cb08e44
  Matt Arsenault authored Jan 17, 2019
  0cb08e44
- Fix capitalization. NFC · 639e0661
  Diana Picus authored Jan 17, 2019
  639e0661
- [ARM GlobalISel] Allow calls to varargs functions · d5c2499a
  Diana Picus authored Jan 17, 2019
  d5c2499a
- [RISCV] Add codegen support for RV64A · 07f1c623
  Alex Bradbury authored Jan 17, 2019
  07f1c623
- [WebAssembly] Parse llvm.ident into producers section · cbda16eb
  Thomas Lively authored Jan 17, 2019
  cbda16eb
- Revert "[WebAssembly] Parse llvm.ident into producers section" · 3cfcc94c
  Thomas Lively authored Jan 17, 2019
  3cfcc94c
- [SEH] [ARM64] Retrieve the frame pointer from SEH funclets · 685565ae
  Sanjin Sijaric authored Jan 17, 2019
  685565ae
- [WebAssembly] Parse llvm.ident into producers section · a56c23c5
  Thomas Lively authored Jan 16, 2019
  a56c23c5
Jan 16, 2019
- [WebAssembly] Remove expected failure from known_gcc_test_failures.txt. NFC. · 3a2028f4
  Sam Clegg authored Jan 16, 2019
  3a2028f4
- [X86] Sink complex MCU CC helper to .cpp file from .h file, NFC · ca16e9d8
  Reid Kleckner authored Jan 16, 2019
  ca16e9d8
- [X86] Add X86ISD::VSHLV and X86ISD::VSRLV nodes for psllv and psrlv · 59abdf5f
  Craig Topper authored Jan 16, 2019
  59abdf5f
- [X86] Use X86ISD::BLENDV for blendv intrinsics. Replace vselect with blendv... · 5ea31207
  Craig Topper authored Jan 16, 2019
  5ea31207
- AMDGPU: Adjust the chain for loads writing to the HI part of a register. · fe9269f8
  Changpeng Fang authored Jan 16, 2019
  fe9269f8
- [X86] Add a one use check to the setcc inversion code in combineVSelectWithAllOnesOrZeros · e5b7cc8a
  Craig Topper authored Jan 16, 2019
  e5b7cc8a
- [COFF, ARM64] Implement support for SEH extensions __try/__except/__finally · 33c49c0c
  Mandeep Singh Grang authored Jan 16, 2019
  33c49c0c
- [Hexagon] Do not promote terminator instructions in Hexagon loop idioms · 4121eaf0
  Krzysztof Parzyszek authored Jan 16, 2019
  4121eaf0
- [X86][BtVer2] Update latency of horizontal operations. · c5f0f530
  Andrea Di Biagio authored Jan 16, 2019
  c5f0f530
- [X86] getFauxShuffleMask - bail for non-byte aligned shuffle types · 5a2bbe26
  Simon Pilgrim authored Jan 16, 2019
  5a2bbe26
- [X86] Add combineX86ShufflesRecursively helper. NFCI. · 524daea4
  Simon Pilgrim authored Jan 16, 2019
  524daea4
- AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap · c5cec5e1
  Marek Olsak authored Jan 16, 2019
  c5cec5e1
- [x86] lower shuffle of extracts to AVX2 vperm instructions · 0dbecd05
  Sanjay Patel authored Jan 16, 2019
  0dbecd05
- [MSP430] Emit a separate section for every interrupt vector · cbdb4eff
  Anton Korobeynikov authored Jan 16, 2019
  cbdb4eff
- [GISel]: Add support for CSEing continuously during GISel passes. · 500e3ead
  Aditya Nandakumar authored Jan 16, 2019
  500e3ead