Commits · d8b51789fd63491ae806f53f43df8d2024dbaf19 · Roger Ferrer / llvm-epi · GitLab

Apr 01, 2020
- [NFC] [PowerPC] Add test for frsp elimination · d8b51789
  Qiu Chaofan authored Apr 01, 2020
  
  d8b51789
- [X86] Do not assume types are legal in getFauxShuffleMask · ef49895d
  Bjorn Pettersson authored Mar 31, 2020
  ef49895d
- [DAGCombiner] Require ninf for sqrt recip estimation · 95bcab82
  Qiu Chaofan authored Apr 01, 2020
  95bcab82
- [X86][AVX] Add additional 256/512-bit test cases for PACKSS/PACKUS shuffle patterns · f9f401db
  Simon Pilgrim authored Mar 31, 2020
  f9f401db
- [X86] Run XOP vector rotation tests with/without AVX2 · 3c9064ed
  Simon Pilgrim authored Mar 31, 2020
  3c9064ed
- [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled · 8eb40e41
  Kai Luo authored Apr 01, 2020
  8eb40e41
- AMDGPU/GlobalISel: Fix insert point when lowering G_FMAD · 43e57659
  Matt Arsenault authored Mar 31, 2020
  
  43e57659
- [PPCInstPrinter] Print conditional branches as `bt 2, $target` instead of `bt 2, .+$imm` · 4af7560b
  Fangrui Song authored Mar 26, 2020
  4af7560b
Mar 31, 2020
- [Object] Update ObjectFile::makeTriple for XCOFF · 478af447
  Hubert Tong authored Mar 31, 2020
  478af447
- [AArch64] Change AArch64 Windows EH UnwindHelp object to be a fixed object · 494abe13
  Daniel Frampton authored Mar 31, 2020
  494abe13
- [AArch64] Fix mismatch in prologue and epilogue for funclets on Windows · 522b4c4b
  Daniel Frampton authored Mar 31, 2020
  522b4c4b
- [AArch64][SVE] Add support for fcmp. · dacf8d35
  Eli Friedman authored Mar 26, 2020
  dacf8d35
- [AMDGPU] Define 16 bit VGPR subregs · 08682dcc
  Stanislav Mekhanoshin authored Feb 05, 2020
  08682dcc
- [X86][SSE] Add additional PTEST/TESTP inversion tests · 30436a1c
  Simon Pilgrim authored Mar 31, 2020
  
  30436a1c
- [X86][SSE] Simplify PTEST/TESTP tests for D76984 · 8b925440
  Simon Pilgrim authored Mar 31, 2020
  8b925440
- [SystemZ] Improve foldMemoryOperandImpl(). · f481d488
  Jonas Paulsson authored Mar 17, 2020
  f481d488
- Revert rGefe59d6717dcdf7777acb9b7a734e1a520bdf22a "[X86][SSE]... · 7e0e5fa4
  Simon Pilgrim authored Mar 31, 2020
  7e0e5fa4
- [X86][SSE] lowerShuffleWithPACK - extend to use chained PACKs for larger truncations · efe59d67
  Simon Pilgrim authored Mar 31, 2020
  efe59d67
- [X86] Combine concat(palignr,palignr) -> palignr(concat,concat) · 98357dee
  Simon Pilgrim authored Mar 31, 2020
  98357dee
- [ARM] Fix qdadd operand order · 2c5f43f9
  David Green authored Mar 30, 2020
  2c5f43f9
- [AMDGPU] New llvm.amdgcn.ballot intrinsic · 5d3a69fe
  Sebastian Neubauer authored Mar 05, 2020
  5d3a69fe
- [RISCV] ELF attribute section for RISC-V. · 581ba352
  Kai Wang authored Feb 04, 2020
  581ba352
- [Mips] Make MipsBranchExpansion aware of BBIT family of branch · bcbd60ae
  Djordje Todorovic authored Mar 27, 2020
  bcbd60ae
- [AVR] Generalize the previous interrupt bugfix to signal handlers too · 7b808b10
  Dylan McKay authored Mar 31, 2020
  
  7b808b10
- [AVR] Respect the 'interrupt' function attribute · 339b3426
  Dylan McKay authored Mar 31, 2020
  339b3426
- [PowerPC] Don't do the folding if the operand is R0/X0 · 4eeb56d0
  QingShan Zhang authored Mar 31, 2020
  4eeb56d0
- [GlobalISel] Implement identity transforms for x op x -> x · d5ee7206
  Jessica Paquette authored Mar 30, 2020
  d5ee7206
- [LegalizeTypes] Add SoftenFloatRes_FREEZE · 519f5c37
  Juneyoung Lee authored Mar 28, 2020
  519f5c37
- [GlobalISel] Combine (x op 0) -> x for operations with a right identity of 0 · 63d70ea6
  Jessica Paquette authored Mar 23, 2020
  63d70ea6
- Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types" · b8fc192d
  Matt Arsenault authored Feb 17, 2020
  b8fc192d
Mar 30, 2020
- AMDGPU: Form v_cvt_ubyte* with f16 results · db9f0d1c
  Matt Arsenault authored Mar 29, 2020
  db9f0d1c
- AMDGPU/GlobalISel: Form CVT_F32_UBYTE0 · b27d255e
  Matt Arsenault authored Mar 25, 2020
  
  b27d255e
- AMDGPU/GlobalISel: Handle image atomics · bcb643c8
  Matt Arsenault authored Feb 08, 2020
  
  bcb643c8
- AMDGPU/GlobalISel: Start selecting image intrinsics · 48eda372
  Matt Arsenault authored Feb 07, 2020
  48eda372
- AMDGPU: Account for dmask when computing image mem size · 570a578e
  Matt Arsenault authored Jan 28, 2020
  570a578e
- AMDGPU: Implement getMemcpyLoopLoweringType · cee65d51
  Jay Foad authored Mar 30, 2020
  cee65d51
- AMDGPU/GlobalISel: Round up image operations with 5, 6 or 7 addresses · 2641ba52
  Matt Arsenault authored Feb 08, 2020
  2641ba52
- AMDGPU/GlobalISel: Start handling _L to _LZ optimization · 42d56098
  Matt Arsenault authored Feb 08, 2020
  42d56098
- AMDGPU/GlobalISel: Basic legalize rules for G_FSHR · 4919f2e1
  Matt Arsenault authored Mar 19, 2020
  4919f2e1
- GlobalISel: Translate llvm.fshl/llvm.fshr · 23da702d
  Matt Arsenault authored Mar 19, 2020
  
  23da702d