Commits · d8f9eaad89fa895bf665564310a803f7fa168d81 · Roger Ferrer / llvm-epi · GitLab

Dec 01, 2021
- [RISCV] Teach RISCVTargetLowering::shouldSinkOperands to handle udiv/sdiv/urem/srem. · d8f9eaad
  Craig Topper authored Nov 30, 2021
  d8f9eaad
Nov 30, 2021
- Big-endian version of vpermxor · 0850655d
  Tarique Islam authored Nov 30, 2021
  0850655d
- AArch64 GIsel: legalize lshr operands, even if it is poison · 18308e17
  Jameson Nash authored Nov 30, 2021
  18308e17
- Typo fix · c0b33a65
  Hans Wennborg authored Nov 30, 2021
  
  c0b33a65
- Revert "Use VersionTuple for parsing versions in Triple. This makes it... · 40d5eeac
  Nikita Popov authored Nov 30, 2021
  40d5eeac
- Code quality: Combine V_RSQ · ca57b80c
  Mateja Marjanovic authored Sep 20, 2021
  ca57b80c
- Use VersionTuple for parsing versions in Triple. This makes it possible to... · 1e828646
  James Farrell authored Nov 16, 2021
  1e828646
- [DAG] Create fptosi.sat from clamped fptosi · 9e8a71ca
  David Green authored Nov 30, 2021
  9e8a71ca
- Revert "[DAG] Create fptosi.sat from clamped fptosi" · a87782c3
  Hans Wennborg authored Nov 30, 2021
  a87782c3
- [DebugInfo][InstrRef][X86] Instrument expanded DYN_ALLOCAs · 7093c810
  Jeremy Morse authored Nov 30, 2021
  7093c810
- [AMDGPU][NFC] Remove unused defvar in AMDGPUInstructions.td. · 14c40511
  Abinav Puthan Purayil authored Nov 30, 2021
  
  14c40511
- [DAG] Create fptosi.sat from clamped fptosi · 52ff3b00
  David Green authored Nov 30, 2021
  52ff3b00
- [clang][ARM] PACBTI-M assembly support · 5cff77c2
  Ties Stuij authored Nov 30, 2021
  5cff77c2
- [RISCV] Decode vtype with reserved fields to raw immediate · 29d4230d
  Ben Shi authored Nov 25, 2021
  29d4230d
- [X86][LoopVectorize] "Fix" `X86TTIImpl::getAddressComputationCost()` · 8cd78248
  Roman Lebedev authored Nov 30, 2021
  8cd78248
- [ARM] create new pseudo t2LDRLIT_ga_pcrel for stack guards · 89453ed6
  Nick Desaulniers authored Nov 30, 2021
  89453ed6
- [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc · 5297cbf0
  Christudasan Devadasan authored Sep 06, 2021
  5297cbf0
- [RISCV] Promote f16 log/pow/exp/sin/cos/etc. to f32 libcalls. · b121d23a
  Craig Topper authored Nov 29, 2021
  b121d23a
- [RISCV] Fix a bug in RISCVFrameLowering. · 9a885665
  Hsiangkai Wang authored Nov 19, 2021
  9a885665
- [NFC] Header comment in X86RegisterBanks.td referred to Aarch64 · fde93774
  Mircea Trofin authored Nov 29, 2021
  fde93774
- X86: Fold masked-merge when and-not is not available · 87ba99c2
  Matthias Braun authored Oct 15, 2021
  87ba99c2
Nov 29, 2021
- [llvm] Use range-based for loops (NFC) · f240e528
  Kazu Hirata authored Nov 29, 2021
  
  f240e528
- [X86][Costmodel] `getInterleavedMemoryOpCostAVX512()`: masked load can not be folded into a shuffle · 7e73c2a6
  Roman Lebedev authored Nov 29, 2021
  7e73c2a6
- [AMDGPU][GlobalISel] Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) · 89511362
  Mirko Brkusanin authored Nov 26, 2021
  89511362
- [AMDGPU][GlobalISel] Transform (fadd (fmul x, y), z) -> (fma x, y, z) · 881840fc
  Mirko Brkusanin authored Nov 26, 2021
  881840fc
- [CodeGen][AArch64] Bail out in performConcatVectorsCombine for scalable vectors · 84364bda
  David Sherwood authored Nov 25, 2021
  84364bda
- [AArch64][SVE] Mark fixed-type FP extending/truncating loads/stores as custom · 61808066
  Bradley Smith authored Nov 24, 2021
  61808066
- [X86][Costmodel] Now that `getReplicationShuffleCost()` is good, update... · cffe3a08
  Roman Lebedev authored Nov 29, 2021
  cffe3a08
- [CodeGen][SVE] Use whilelo instruction when lowering @llvm.get.active.lane.mask · a31f4bdf
  David Sherwood authored Nov 23, 2021
  a31f4bdf
- [llvm] Use range-based for loops (NFC) · fd7d4064
  Kazu Hirata authored Nov 28, 2021
  
  fd7d4064
Nov 28, 2021
- [llvm] Use range-based for loops (NFC) · c73fc74c
  Kazu Hirata authored Nov 28, 2021
  
  c73fc74c
Nov 27, 2021
- [ARM] CSINC/CSINV patterns from CMOV · 5c64d8ef
  David Green authored Nov 27, 2021
  5c64d8ef
- [Target] Use range-based for loops (NFC) · ff649e08
  Kazu Hirata authored Nov 27, 2021
  
  ff649e08
- [ARM] Fold away unnecessary CSET/CMPZ · 7d5d063c
  David Green authored Nov 27, 2021
  7d5d063c
- [NVPTX][AsmPrinter] Avoid removing globals before calling AsmPrinter::doFinalization() · 9f374a74
  Kristina Bessonova authored Nov 27, 2021
  9f374a74
- [RISCV] Emit DWARF location expression for RVV stack objects. · b0c74215
  Hsiangkai Wang authored Aug 04, 2021
  b0c74215
- [Target] Use range-based for loops (NFC) · 387927bb
  Kazu Hirata authored Nov 26, 2021
  
  387927bb
Nov 26, 2021
- [Target] Use range-based for loops (NFC) · 562356d6
  Kazu Hirata authored Nov 26, 2021
  
  562356d6
- [AArch64][SVEIntrinsicOpts] Fix: predicated SVE mul/fmul are not commutative · 08d45e6f
  Igor Kirillov authored Nov 24, 2021
  08d45e6f
- [AMDGPU] Add SIMemoryLegalizer comments to clarify bit usage · 8967d044
  Carl Ritson authored Nov 26, 2021
  8967d044