Commits · d9dfc2e752c959e0fbf7b642f09392ff32f5b522 · Roger Ferrer / llvm-epi · GitLab

Nov 02, 2009
- Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should · d9dfc2e7
  Kevin Enderby authored Nov 02, 2009
  d9dfc2e7
- Fix schedule model for BFC. · 5ac6f244
  David Goodwin authored Nov 02, 2009
  5ac6f244
- Hyphenate some comments. · 4c00a524
  Bob Wilson authored Nov 02, 2009
  4c00a524
- Add support for BlockAddress values in ARM constant pools. · 433ab09c
  Bob Wilson authored Nov 02, 2009
  433ab09c
- Prune unnecessary include. · e90a4aa7
  Bob Wilson authored Nov 02, 2009
  e90a4aa7
- These are done / no longer care. · 115cfc07
  Evan Cheng authored Nov 02, 2009
  115cfc07
- Add an entry. · f6f1b37f
  Evan Cheng authored Nov 02, 2009
  f6f1b37f
- Unbreak ARMBaseRegisterInfo::copyRegToReg. · 1708b06c
  Evan Cheng authored Nov 02, 2009
  1708b06c
- Handle splats of undefs properly. This includes the testcase for PR5364 as well. · 4d23754b
  Anton Korobeynikov authored Nov 02, 2009
  4d23754b
- Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this... · 0f38d989
  Anton Korobeynikov authored Nov 02, 2009
  0f38d989
- 64-bit FP loads & stores operate on both NEON and VFP pipelines. · 8cce1eb6
  Anton Korobeynikov authored Nov 02, 2009
  8cce1eb6
- Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls,... · 14635da9
  Anton Korobeynikov authored Nov 02, 2009
  14635da9
Nov 01, 2009
- Fix a couple more places where we are creating ld / st instructions without memoperands. · 1a4492be
  Evan Cheng authored Nov 01, 2009
  1a4492be
- Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. · 43219997
  Evan Cheng authored Nov 01, 2009
  43219997
- Use cbz and cbnz instructions. · 6f29ad91
  Evan Cheng authored Oct 31, 2009
  6f29ad91
Oct 31, 2009
- vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using · 5cba8de2
  Jim Grosbach authored Oct 31, 2009
  5cba8de2
- Expand 64-bit logical shift right inline · 8fe6fd70
  Jim Grosbach authored Oct 31, 2009
  8fe6fd70
- Expand 64-bit arithmetic shift right inline · 624fcb28
  Jim Grosbach authored Oct 31, 2009
  624fcb28
- Expand 64 bit left shift inline rather than using the libcall. For now, this · 5d994048
  Jim Grosbach authored Oct 31, 2009
  5d994048
- It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable... · cdbb70c0
  Evan Cheng authored Oct 31, 2009
  cdbb70c0
Oct 30, 2009
- Updates to the ARM target assembler for llvm-mc per review comments from · 8be42bd0
  Kevin Enderby authored Oct 30, 2009
  8be42bd0
- Add a note about Robert Muth's alternate jump table implementation. · c7415bf5
  Bob Wilson authored Oct 30, 2009
  c7415bf5
- Fix a comment. · 6b00f4b7
  Bob Wilson authored Oct 30, 2009
  6b00f4b7
- This fixes functions like · ab7c709f
  Rafael Espindola authored Oct 30, 2009
  ab7c709f
- Add ARM codegen for indirect branches. · 1cf0b030
  Bob Wilson authored Oct 30, 2009
  1cf0b030
- Dial back the realignment a bit. · 85780683
  Jim Grosbach authored Oct 30, 2009
  85780683
Oct 29, 2009
- Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a · 453d64c9
  Dan Gohman authored Oct 29, 2009
  453d64c9
- To get more thorough testing from llc-beta nightly runs, do dynamic stack · b352d764
  Jim Grosbach authored Oct 29, 2009
  b352d764
Oct 28, 2009
- Revert r85346 change to control tail merging by CodeGenOpt::Level. · 97b93126
  Bob Wilson authored Oct 28, 2009
  97b93126
- Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the · 73789b84
  Bob Wilson authored Oct 28, 2009
  73789b84
- fconsts and fconstd are obviously re-materializable. · 6203c686
  Evan Cheng authored Oct 28, 2009
  6203c686
- Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. · 294aea70
  Jim Grosbach authored Oct 28, 2009
  294aea70
- Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. · ec6d7c94
  Evan Cheng authored Oct 28, 2009
  ec6d7c94
- Use fconsts and fconstd to materialize small fp constants. · 4a609f3c
  Evan Cheng authored Oct 28, 2009
  4a609f3c
- Add an indirect branch pattern for ARM. Testcase will be coming soon. · e4b80c9b
  Bob Wilson authored Oct 28, 2009
  e4b80c9b
- Record CodeGen optimization level in the BranchFolding pass so that we can · 9693f9d4
  Bob Wilson authored Oct 27, 2009
  9693f9d4
Oct 27, 2009
- Enable virtual register based frame index scavenging by default for ARM & T2. · 5607d2cb
  Jim Grosbach authored Oct 27, 2009
  5607d2cb
- Infrastructure for dynamic stack realignment on ARM. For now, this is off by · c1403a00
  Jim Grosbach authored Oct 27, 2009
  c1403a00
- Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. · cde65ec5
  Johnny Chen authored Oct 27, 2009
  cde65ec5
- Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between · 4f36affe
  Johnny Chen authored Oct 27, 2009
  4f36affe