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Commits · d9ebff8bab3b4948f281b7d83872da0f2424de14

llvm-epi
llvm
test
CodeGen
Mips
fastcc.ll

Mar 13, 2015
- [opaque pointer type] Add textual IR support for explicit type parameter to gep operator · f72d05bc
  David Blaikie authored Mar 13, 2015
  f72d05bc
Feb 27, 2015
- [opaque pointer type] Add textual IR support for explicit type parameter to load instruction · a79ac14f
  David Blaikie authored Feb 27, 2015
  a79ac14f
Nov 07, 2014
- [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... · c43cda84
  Daniel Sanders authored Nov 07, 2014
  c43cda84
Aug 22, 2014
- [mips] Don't use odd-numbered float registers for double arguments for fastcc · 86ebfe24
  Sasa Stankovic authored Aug 22, 2014
  86ebfe24
Jul 29, 2014
- [mips] Don't use odd-numbered single precision registers for fastcc calling · f4a9e3bc
  Sasa Stankovic authored Jul 29, 2014
  f4a9e3bc
Feb 07, 2014
- [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl. · 4c80bdae
  Sasa Stankovic authored Feb 07, 2014
  4c80bdae
Jun 13, 2012
- Implement fastcc calling convention for MIPS. · f0273603
  Akira Hatanaka authored Jun 13, 2012
  f0273603

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