Commits · db4d6ef9efccb2781b4a2bb64eba0f40d0a8eec3 · Roger Ferrer / llvm-epi · GitLab

Aug 01, 2023
- AMDGPU: Directly emit fabs intrinsic instead of new libcall · db4d6ef9
  Matt Arsenault authored Jul 31, 2023
  
  db4d6ef9
- AMDGPU/GlobalISel: Use SGPR results for G_AMDGPU_WAVE_ADDRESS · 0aa439d5
  Matt Arsenault authored Jul 30, 2023
  
  0aa439d5
Jul 31, 2023
- [BPF] Clean up SelLowering · d542a56c
  Tamir Duberstein authored Jul 31, 2023
  d542a56c
- AMDGPU: Move check of compatible libcall · f63cdfc4
  Matt Arsenault authored Jul 30, 2023
  f63cdfc4
- [AArch64] Add some basic handling for bf16 constants. · 778fa4ed
  David Green authored Jul 31, 2023
  778fa4ed
- [RISCV] Add a common base class for RVInstR variations. NFC · fb97316b
  Craig Topper authored Jul 31, 2023
  fb97316b
- [RISCV] Add a common base class for RVInstI variations. NFC · f92dc108
  Craig Topper authored Jul 31, 2023
  f92dc108
- [AMDGPU] AMDGPUTargetStreamer::getArchNameFromElfMach - use GPUKind::GK_NONE... · 17ecb55d
  Simon Pilgrim authored Jul 31, 2023
  17ecb55d
- [X86] Allow pre-SSE41 targets to extract multiple v16i8 elements coming from... · 071671e1
  Simon Pilgrim authored Jul 31, 2023
  071671e1
- AMDGPU: Don't store current instruction in AMDGPULibCalls member · c2c22c6c
  Matt Arsenault authored Jul 30, 2023
  c2c22c6c
- AMDGPU: Refactor libcall simplify to help with future refined fast math flag usage · 8f381380
  Matt Arsenault authored Jul 30, 2023
  8f381380
- AMDGPU: Don't parse name of sin/cos twice in libcall simplify · 94d55450
  Matt Arsenault authored Jul 30, 2023
  
  94d55450
- AMDGPU: Partially respect nobuiltin in libcall simplifier · 8a677a7f
  Matt Arsenault authored Jul 30, 2023
  8a677a7f
- AMDGPU: Some AMDGPULibCalls cleanups · 2dc1a274
  Matt Arsenault authored Jul 30, 2023
  2dc1a274
- GlobalISel: Pass MachineIRBuilder to applyMappingImpl · d6f9428e
  Matt Arsenault authored Aug 09, 2020
  d6f9428e
- [SystemZ] Replace OperandMatchResultTy with ParseStatus (NFC) · aeeaadd6
  Sergei Barannikov authored Jul 03, 2023
  aeeaadd6
- AMDGPU: Simplify early exit handling for libcall simplify · ab6cd2d4
  Matt Arsenault authored Jul 30, 2023
  ab6cd2d4
- AMDGPU: Adjust outdated comment · 055a7f25
  Matt Arsenault authored Jul 29, 2023
  
  055a7f25
- AMDGPU: Use available subtarget member · 51ec5a27
  Matt Arsenault authored Jul 29, 2023
  
  51ec5a27
- AMDGPU: Remove some typed pointer handling · 360a5d56
  Matt Arsenault authored Jul 30, 2023
  
  360a5d56
- [X86] LowerEXTRACT_VECTOR_ELT - match i8 extraction with MVT::i8 instead of getSizeInBits() · c1c86f9e
  Simon Pilgrim authored Jul 31, 2023
  c1c86f9e
- [RISCV] Fix typo in C9LeftShift · 19a1b67b
  Pengcheng Wang authored Jul 31, 2023
  19a1b67b
- [GlobalISel] convergent intrinsics · d9847cde
  Sameer Sahasrabuddhe authored Jul 31, 2023
  d9847cde
- [RISCV] Clean up RISCVInstrInfoXTHead.td to look like the same style with other td file. NFC. · f2e44238
  Jim Lin authored Jul 31, 2023
  f2e44238
- [AArch64][GlobalISel] G_FMINNUM and G_FMAXNUM vector lowering · e8e49a35
  David Green authored Jul 31, 2023
  e8e49a35
- [RISCV] Combine setOperationAction code for ISD::CTLZ for Zbb and XTheadBB. NFC · 56b54eda
  Craig Topper authored Jul 30, 2023
  56b54eda
- [CSKY] Add more IR patterns to select FNMUL · 14e0a67a
  Ben Shi authored Jul 13, 2023
  14e0a67a
- [RISCV] Use x0 in vsetvli when avl is equal to vlmax. · b7408ebb
  Jianjian GUAN authored Jul 27, 2023
  b7408ebb
Jul 30, 2023
- [RISCV] Simplify some predicate functions in RISCVSubtarget.h. NFC · 54e8cfe6
  Craig Topper authored Jul 30, 2023
  54e8cfe6
- [RISCV] Rename XTHead DecoderNamespaces to match their extension names include the 'X'. NFC · b4bb111b
  Craig Topper authored Jul 30, 2023
  b4bb111b
- [RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV extensions. NFC · 0c7d8976
  Craig Topper authored Jul 30, 2023
  
  0c7d8976
- [X86] getSingleConstraintMatchWeight - cleanup variable names. NFCI. · 0c5e9064
  Simon Pilgrim authored Jul 30, 2023
  0c5e9064
- [X86] X86DAGToDAGISel::matchAddressRecursively - use... · 6dfa95da
  Simon Pilgrim authored Jul 30, 2023
  6dfa95da
Jul 29, 2023
- [RISCV] Use RVInstIUnary for THRev_r in RISCVInstrInfoXTHead.td. NFC · 20edd990
  Craig Topper authored Jul 28, 2023
  20edd990
- [RISCV] Add RVInstIUnary class to RISCVInstrFormats.td. NFC · 68047165
  Craig Topper authored Jul 28, 2023
  68047165
- [RISCV] Simplify RVKUnary_rnum slightly. NFC · 2f955646
  Craig Topper authored Jul 28, 2023
  
  2f955646
- [RISCV][MC][MSan] Fix uninitialized data members · c956f915
  Jordan Rupprecht authored Jul 28, 2023
  c956f915
Jul 28, 2023
- [AArch64] Change the cost of vector insert/extract to 2 · 2a859b20
  David Green authored Jul 28, 2023
  2a859b20
- [AA] Skip the layer of indirection in returning conservative results. · d020fa2b
  David Goldblatt authored Apr 24, 2023
  d020fa2b
- AMDGPU/GlobalISel: Set dead on scc on manually selected instructions · 3240ae70
  Matt Arsenault authored Jul 28, 2023
  3240ae70