Commits · dcc5ff3bc2e85a07ff2192223c652fa2cdb164ef · Roger Ferrer / llvm-epi · GitLab

May 11, 2020
- [PowerPC] Use PredictableSelectIsExpensive to enable select to branch in CGP · dcc5ff3b
  Kang Zhang authored May 11, 2020
  dcc5ff3b
- Revert "[DAGCombine] Remove the getNegatibleCost to avoid the out of sync with... · 728cf6d8
  Sam McCall authored May 11, 2020
  728cf6d8
- [DAGCombine] Remove the getNegatibleCost to avoid the out of sync with getNegatedExpression · 3c44c441
  QingShan Zhang authored May 11, 2020
  3c44c441
- [X86] Fix combineVectorCompareAndMaskUnaryOp regression after... · f40fc7b8
  Fangrui Song authored May 10, 2020
  f40fc7b8
May 10, 2020
- [X86] Add a few more shuffles to hasUndefRegUpdate. · e4c454b0
  Craig Topper authored May 10, 2020
  e4c454b0
- GlobalISel: Handle more cases in lowerUnmergeValues · 3af85fa8
  Matt Arsenault authored Mar 29, 2020
  3af85fa8
May 09, 2020
- [X86] isVectorShiftByScalarCheap - don't limit fast XOP vector shifts to 128-bit vectors · 9237d880
  Simon Pilgrim authored May 09, 2020
  9237d880
- GlobalISel: Move code into lowering for G_MERGE_VALUES · 69999605
  Matt Arsenault authored Mar 29, 2020
  69999605
- AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory · beda9d04
  Matt Arsenault authored May 08, 2020
  beda9d04
- [X86] Teach getUndefRegClearance that we use undef for inputs to PUNPCK in some cases. · c7be6a86
  Craig Topper authored May 09, 2020
  c7be6a86
- [X86] Add an assert that v32i16/v64i8 splitting in LowerVSETCC should only... · 56bf0b58
  Craig Topper authored May 09, 2020
  56bf0b58
- [ARM] Convert VDUPLANE to VDUP under MVE · 6eee2d9b
  David Green authored May 09, 2020
  6eee2d9b
- [X86] Allow combineVectorCompareAndMaskUnaryOp to handle 'all-bits' general case · 0e8e7314
  Simon Pilgrim authored May 09, 2020
  0e8e7314
- [NFC] Clean up in MCObjectStreamer and X86AsmBackend · 99ac9ce7
  Shengchen Kan authored May 09, 2020
  
  99ac9ce7
- [SelectionDAG] Remove ConstantPoolSDNode::getAlignment. · bebdc62c
  Craig Topper authored May 08, 2020
  bebdc62c
- [SelectionDAG] Use Align/MaybeAlign for ConstantPoolSDNode. · d1119980
  Craig Topper authored May 08, 2020
  d1119980
- [AMDGPU] Vectorize alloca thru bitcast · db7dea2b
  Stanislav Mekhanoshin authored May 05, 2020
  db7dea2b
May 08, 2020
- [WebAssembly] Disallow 'shared-mem' rather than 'atomics' · a1ae9566
  Thomas Lively authored May 06, 2020
  a1ae9566
- [Target][XCOFF] Correctly halt when mixing AIX or XCOFF with ppc64le · 601d5bd5
  Hubert Tong authored May 08, 2020
  601d5bd5
- [AIX] Avoid structor alias; die before bad alias codegen · b116ded5
  Hubert Tong authored May 08, 2020
  b116ded5
- [X86] Add assembler support for {vex} prefix to match GNU as. · adf3b8e3
  Craig Topper authored May 08, 2020
  adf3b8e3
- AMDGPU: Don't assert on unknown address spaces · 78a43f10
  Matt Arsenault authored May 07, 2020
  78a43f10
- AMDGPU: Lower addrspacecast to 32-bit constant · fda0c8df
  Matt Arsenault authored May 07, 2020
  fda0c8df
- [X86][AVX] Don't let X86ISD::BROADCAST peek through bitcasts to illegal types. · 5f9f37c4
  Simon Pilgrim authored May 08, 2020
  5f9f37c4
- [AMDGPU] Try to determine sign bit during div/rem expansion · 5fa87ec0
  Nikita Popov authored May 07, 2020
  5fa87ec0
May 07, 2020
- [X86][AVX] combineSignExtendInReg - promote mask arithmetic before v4i64 canonicalization · b8a72527
  Simon Pilgrim authored May 07, 2020
  b8a72527
- [ARM][MVE] Add support for incrementing gathers · 1e413a8c
  Anna Welker authored May 07, 2020
  1e413a8c
- [VE] Minimum MC layer for VE (2/4) · 447efdb5
  Kazushi (Jam) Marukawa authored May 07, 2020
  447efdb5
- [VE] Implements minimum MC layer for VE (1/4) · 6999ffcc
  Kazushi (Jam) Marukawa authored May 07, 2020
  6999ffcc
- [CodeGen][SVE] Lowering of shift operations with scalable types · 3bcd3dd4
  Kerry McLaughlin authored May 07, 2020
  3bcd3dd4
- [AMDGPU] Cluster shader exports · e3ffe726
  Carl Ritson authored May 07, 2020
  e3ffe726
- [X86] Enable combinePMULH to match multiplies with elements larger than i32. · 35064559
  Craig Topper authored May 06, 2020
  35064559
- [AArch64][SVE] Implement lowering for SIGN_EXTEND etc. of SVE predicates. · 2c854610
  Eli Friedman authored Apr 29, 2020
  2c854610
May 06, 2020
- [X86] Remove support for Y0 constraint as an alias for Yz in inline assembly. · 16c800b8
  Craig Topper authored May 06, 2020
  16c800b8
- [X86] Remove incomplete support for 'Y' has an inline assembly constraint by itself. · 9bb9ff09
  Craig Topper authored May 06, 2020
  9bb9ff09
- [SystemZ] Fix/optimize vec_load_len and related intrinsics · 947f78ac
  Ulrich Weigand authored May 06, 2020
  947f78ac
- [amdgpu] Fix check of VCC. · 4ee5a041
  Michael Liao authored May 06, 2020
  4ee5a041
- [X86] getShuffleScalarElt - add CONCAT_VECTORS/INSERT_VECTOR_ELT support. · 8817334c
  Simon Pilgrim authored May 06, 2020
  8817334c
- [X86] getShuffleScalarElt - consistently use SDValue. NFC. · 8c71c229
  Simon Pilgrim authored May 06, 2020
  8c71c229
- [AMDGPU] Drop 16 bit subreg suffixes on print · 54d6dfe9
  Stanislav Mekhanoshin authored May 05, 2020
  54d6dfe9