Commits · dcde6e30b9663983fe31acb24b21cc2812e9b5ed · Roger Ferrer / llvm-epi · GitLab

Sep 12, 2011
- Mark LDWCP as having no side effects. · dcde6e30
  Richard Osborne authored Sep 12, 2011
  dcde6e30
- Format patterns, remove unused X86blend patterns · c0c71e16
  Nadav Rotem authored Sep 12, 2011
  c0c71e16
- Fix disassembling of one of the register/register forms of... · 48f2b369
  Craig Topper authored Sep 11, 2011
  48f2b369
Sep 11, 2011
- Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. · a88e3560
  Craig Topper authored Sep 11, 2011
  a88e3560
- CR fixes per Bruno's request. · b873b187
  Nadav Rotem authored Sep 11, 2011
  b873b187
Sep 10, 2011
- r139454 activates an assert in a case where we were doing the right thing... · 7f50e002
  Eli Friedman authored Sep 10, 2011
  7f50e002
- Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and · 74996f2a
  Richard Trieu authored Sep 10, 2011
  74996f2a
- Fixed an assert from: · d9917bef
  Richard Trieu authored Sep 10, 2011
  d9917bef
- Thumb2 parsing and encoding for MOV(immediate). · b908b7af
  Jim Grosbach authored Sep 10, 2011
  b908b7af
- LDM writeback is not allowed if Rn is in the target register list. · 53db43b5
  Owen Anderson authored Sep 09, 2011
  53db43b5
- Fix an ambiguously nested if. · eb3f0fbd
  Owen Anderson authored Sep 09, 2011
  eb3f0fbd
- Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB. · 93cd3186
  Owen Anderson authored Sep 09, 2011
  93cd3186
- Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. · 5bfb0e0a
  Owen Anderson authored Sep 09, 2011
  5bfb0e0a
- O64 will not be supported. · 8b983d97
  Akira Hatanaka authored Sep 09, 2011
  8b983d97
- Make F31 and D15 non-reserved registers. · be159b5f
  Akira Hatanaka authored Sep 09, 2011
  be159b5f
Sep 09, 2011
- Thumb unconditional branches are allowed in IT blocks, and therefore should... · 29cfe6c3
  Owen Anderson authored Sep 09, 2011
  29cfe6c3
- Mips32 does not reserve even-numbered floating point registers. · 9d5f9278
  Akira Hatanaka authored Sep 09, 2011
  9d5f9278
- Drop support for Mips1 and Mips2. · 4444daee
  Akira Hatanaka authored Sep 09, 2011
  4444daee
- Implement vector-select support for avx256. Refactor the vblend implementation... · de838dae
  Nadav Rotem authored Sep 09, 2011
  de838dae
- Thumb2 assembly parsing and encoding for MLA and MLS. · 62c33955
  Jim Grosbach authored Sep 09, 2011
  62c33955
- Thumb2 assembly parsing and encoding for LDRSB. · 779a2bee
  Jim Grosbach authored Sep 09, 2011
  779a2bee
- Drop support for Allegrex. Allegrex implements a variant of Mips2. · d22a1c6c
  Akira Hatanaka authored Sep 09, 2011
  d22a1c6c
- Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. · a05627eb
  Jim Grosbach authored Sep 09, 2011
  a05627eb
- Fix handling of Intel syntax disassembling of movs and stos to stop being... · 5d513401
  Craig Topper authored Sep 09, 2011
  5d513401
- Change default target architecture from Mips1 to Mips32r1 in preparation for · df1df7ed
  Akira Hatanaka authored Sep 09, 2011
  df1df7ed
- 80 columns. · 83dee99c
  Akira Hatanaka authored Sep 09, 2011
  83dee99c
- All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. · 33d39536
  Owen Anderson authored Sep 08, 2011
  33d39536
- Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. · 2fefa427
  Owen Anderson authored Sep 08, 2011
  2fefa427
- Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types. · b5df6203
  Nadav Rotem authored Sep 08, 2011
  b5df6203
- Thumb2 assembly parsing and encoding for LDRD(immediate). · 7db8d697
  Jim Grosbach authored Sep 08, 2011
  7db8d697
Sep 08, 2011
- Add a AVX version of a simple i64 -> f64 bitcast. This could be · 46b9cde0
  Bruno Cardoso Lopes authored Sep 08, 2011
  46b9cde0
- * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a · 23eb5265
  Bruno Cardoso Lopes authored Sep 08, 2011
  23eb5265
- Add AVX versions of blend vector operations and fix some issues noticed · fb113a00
  Bruno Cardoso Lopes authored Sep 08, 2011
  fb113a00
- Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. · ea8d803b
  Bruno Cardoso Lopes authored Sep 08, 2011
  ea8d803b
- Add X86-SSE4 codegen support for vector-select. · 2550ba2a
  Nadav Rotem authored Sep 08, 2011
  2550ba2a
- Thumb2 assembly parsing and encoding for LDR post-indexed. · 3343da54
  Jim Grosbach authored Sep 08, 2011
  3343da54
- Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. · c086f689
  Jim Grosbach authored Sep 08, 2011
  c086f689
- Remove the "common" set of instructions shared between ARM and Thumb2 modes. ... · f1749592
  Owen Anderson authored Sep 08, 2011
  f1749592
- Thumb2 assembly parsing and encoding for LDRBT. · 2392c53e
  Jim Grosbach authored Sep 07, 2011
  2392c53e
- Thumb2 assembly parsing and encoding for LDR(register). · e0ebc1c3
  Jim Grosbach authored Sep 07, 2011
  e0ebc1c3