Commits · dce60a747cb7ecad9a6b34e6f6be71cf73c055ec · Roger Ferrer / llvm-epi · GitLab

Nov 19, 2014
- R600/SI: Make SIInstrInfo::isOperandLegal() more strict · e0ddfd11
  Tom Stellard authored Nov 19, 2014
  e0ddfd11
- [mips][micromips] Implement SWM32 and LWM32 instructions · a4c4b5fc
  Zoran Jovanovic authored Nov 19, 2014
  a4c4b5fc
- Vectorize a reduction chain feeding into a 'return' statement. · aba97f4a
  Suyog Sarda authored Nov 19, 2014
  aba97f4a
- [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions. · ffeed441
  Jozef Kolek authored Nov 19, 2014
  ffeed441
- Fix tail recursion elimination · 7b9dc280
  Arnaud A. de Grandmaison authored Nov 19, 2014
  7b9dc280
- [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2. · 4d55b4d7
  Jozef Kolek authored Nov 19, 2014
  4d55b4d7
- [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction. · 73f64eac
  Jozef Kolek authored Nov 19, 2014
  73f64eac
- [mips][microMIPS] Implement LWXS instruction. · 5f95dd2b
  Jozef Kolek authored Nov 19, 2014
  5f95dd2b
- [mips][microMIPS] Implement SDBBP and RDHWR instructions. · dc62fc4a
  Jozef Kolek authored Nov 19, 2014
  dc62fc4a
- [X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2 · 3ac3b251
  Simon Pilgrim authored Nov 19, 2014
  3ac3b251
- AliasSetTracker: UnknownInsts should contribute to the refcount · b7adf34e
  David Majnemer authored Nov 19, 2014
  b7adf34e
- Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> · 70573dcd
  David Blaikie authored Nov 19, 2014
  70573dcd
- [AArch64] Disable useAA for Cortex-A57. · 2aa06a98
  Hao Liu authored Nov 19, 2014
  2aa06a98
- [AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend. · fd46bea4
  Hao Liu authored Nov 19, 2014
  fd46bea4
- [SeparateConstOffsetFromGEP] Allow SeparateConstOffsetFromGEP pass to lower GEPs. · 1d2a061b
  Hao Liu authored Nov 19, 2014
  1d2a061b
- Remove StringMap::GetOrCreateValue in favor of StringMap::insert · 5106ce78
  David Blaikie authored Nov 19, 2014
  5106ce78
- llvm-readobj: fix off-by-one error in COFFDumper · 970dda29
  Rui Ueyama authored Nov 19, 2014
  970dda29
- [Aarch64] Customer lowering of CTPOP to SIMD should check for NEON availability · 7a2d1567
  Weiming Zhao authored Nov 19, 2014
  7a2d1567
- [asan] add experimental basic-block tracing to asan-coverage; also fix... · cb45b126
  Kostya Serebryany authored Nov 19, 2014
  cb45b126
- llvm-readobj: teach it how to dump COFF base relocation table · 74e85130
  Rui Ueyama authored Nov 19, 2014
  74e85130
- Introduce llvm::SplitAllCriticalEdges · e5ea424a
  Kostya Serebryany authored Nov 19, 2014
  e5ea424a
- Revert r222039 because of bot failure. · c6710931
  Manman Ren authored Nov 19, 2014
  c6710931
- R600/SI: Implement areMemAccessesTriviallyDisjoint · c09cc3c5
  Matt Arsenault authored Nov 19, 2014
  c09cc3c5
- R600/SI: Set hasSideEffects = 0 on load and store instructions. · 9a072c19
  Matt Arsenault authored Nov 18, 2014
  9a072c19
- [X86][AVX] 256-bit vector stack unaligned load/stores identification · 9c1e4123
  Simon Pilgrim authored Nov 18, 2014
  9c1e4123
Nov 18, 2014
- [Hexagon] Adding A2_and instruction. · 44fd1c8b
  Colin LeMahieu authored Nov 18, 2014
  44fd1c8b
- [FastISel][AArch64] Also allow folding of sign-/zero-extend and arithmetic · c2508818
  Chad Rosier authored Nov 18, 2014
  c2508818
- [FastISel][AArch64] Also allow folding of sign-/zero-extend and logical · e16d16ae
  Chad Rosier authored Nov 18, 2014
  e16d16ae
- InstCombine: Fix another infinite loop caused by visitFPTrunc · c6b8e20a
  David Majnemer authored Nov 18, 2014
  c6b8e20a
- [Hexagon] Adding A2_sub instruction · 38765e6d
  Colin LeMahieu authored Nov 18, 2014
  38765e6d
- Revert "Revert r222040 because of bot failure." · b32eaddf
  David Majnemer authored Nov 18, 2014
  b32eaddf
- [FastISel][AArch64] Follow-up fix for "Fix shift-immediate emission for "zero" shifts." · cdda9308
  Juergen Ributzka authored Nov 18, 2014
  cdda9308
- R600/SI: Move SIFixSGPRCopies to inst selector passes · 162c1010
  Matt Arsenault authored Nov 18, 2014
  162c1010
- [AArch64] Don't optimize all compare instructions. · 7a7c4684
  Juergen Ributzka authored Nov 18, 2014
  7a7c4684
- Fix an incorrect chain operand when expanding INSERT_VECTOR operations through the stack. · b5a25993
  Owen Anderson authored Nov 18, 2014
  b5a25993
- R600/SI: Make sure resource descriptors are always stored in SGPRs · f0a2107c
  Tom Stellard authored Nov 18, 2014
  f0a2107c
- [Hexagon] Converting from ADD_rr to A2_add which has encoding bits. · efa74e02
  Colin LeMahieu authored Nov 18, 2014
  efa74e02
- [Reassociate] Rename local variable to not use same name as a member · e53e8c8e
  Chad Rosier authored Nov 18, 2014
  e53e8c8e
- [FastISel][AArch64] Fix shift-immediate emission for "zero" shifts. · 4328fd94
  Juergen Ributzka authored Nov 18, 2014
  4328fd94
- Test commit to verify that commit access works. · 52e84e99
  Jozef Kolek authored Nov 18, 2014
  52e84e99