Commits · dd48d3ad0e5fff78e6e3a7fd8ca830624ccb8e33 · Roger Ferrer / llvm-epi · GitLab

Jun 29, 2022
- Revert "[RISCV] Avoid changing etype for splat of 0 or -1" · dd48d3ad
  Philip Reames authored Jun 29, 2022
  dd48d3ad
- [RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C). · 7cbfb4eb
  Craig Topper authored Jun 29, 2022
  7cbfb4eb
- AMDGPU: Make packed 32-bit instructions rematerializable · ffd6aaf5
  Matt Arsenault authored Jun 25, 2022
  
  ffd6aaf5
- AMDGPU: Make 16-bit pk instructions rematerializable · 4c400dc1
  Matt Arsenault authored Jun 25, 2022
  
  4c400dc1
- AMDGPU: Mark more instructions as rematerializable · da6d7728
  Matt Arsenault authored Jun 25, 2022
  da6d7728
- AMDGPU: Use isMeta flags on pseudoinstructions · d342d130
  Matt Arsenault authored Jun 06, 2022
  
  d342d130
- [AArch64][SVE] Match (add x (urshr/srshr y c)) -> ursra/srsra x y c · 424b2ae9
  Bradley Smith authored Jun 17, 2022
  424b2ae9
- [ConstExpr] Remove more leftovers of extractvalue expression (NFC) · 16033ffd
  Nikita Popov authored Jun 29, 2022
  16033ffd
- Pass code-model through Module IR to [llc]. · ff855f5e
  esmeyi authored Jun 29, 2022
  ff855f5e
- [DirectX] Properly fix for MaybeAlign API removal · c967c3d3
  Chris Bieneman authored Jun 28, 2022
  c967c3d3
- [X86][AMX] Split greedy RA for tile register · 5cb09798
  Luo, Yuanke authored Jun 25, 2022
  5cb09798
- [DirectX] Fix broken build after API removal · 072288da
  Chris Bieneman authored Jun 28, 2022
  072288da
- [RISCV] Fold (add X, [-4096, -2049]) or (add X, [2048,4096]) into load/store address during isel. · 5dcc5254
  Craig Topper authored Jun 28, 2022
  5dcc5254
- [AMDGPU] Relax verification of soffset in scalar stores · 21895c6b
  Stanislav Mekhanoshin authored Jun 28, 2022
  21895c6b
- [RISCV] Rename getMin/MaxVLen to getArchMin/MaxVlen and make protected [nfc] · da60558d
  Philip Reames authored Jun 28, 2022
  
  da60558d
- [RISCV] Refine known bits for READ_VLENB · 860c62f5
  Philip Reames authored Jun 28, 2022
  860c62f5
Jun 28, 2022
- [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency · ddc9e886
  Guozhi Wei authored Jun 28, 2022
  ddc9e886
- [RISCV] Teach RISCVMergeBaseOffset to handle read-modify-write of a global. · 02c8453e
  Craig Topper authored Jun 28, 2022
  02c8453e
- [X86] Remove unnecessary COPY from EmitLoweredCascadedSelect. · 3706bdad
  Craig Topper authored Jun 28, 2022
  3706bdad
- [AMDGPU] llvm.amdgcn.exp.compr is not supported on GFX11 · 3fbc945c
  Jay Foad authored Nov 06, 2020
  3fbc945c
- [AMDGPU] Use GFX11 S_PACK_HL instruction in more cases · f1cfaa95
  Joe Nash authored Jun 20, 2022
  f1cfaa95
- [PowerPC] Improve getNormalLoadInput to reach more splat load · 88b6d227
  Ting Wang authored Jun 28, 2022
  88b6d227
- [RISCV] Implement support for the Zicbop extension · 7bcfcabb
  Alex Bradbury authored Jun 28, 2022
  7bcfcabb
- [RISCV] Implement support for the Zicbom and Zicboz extensions · 4f40ca53
  Alex Bradbury authored Jun 28, 2022
  4f40ca53
- [AArch64][SME] Sink tile offset operands into the loop for load/store instructions. · fbefc62a
  Sander de Smalen authored Jun 28, 2022
  fbefc62a
- [AArch64][SME] Add SVE2 psel, uclamp, sclamp and revd IR intrinsics · 054faac9
  David Sherwood authored Jun 21, 2022
  054faac9
- [AArch64][SME] Add SME outer product intrinsics · f916ee0f
  David Sherwood authored Jun 16, 2022
  f916ee0f
- [AArch64][SME] NFC: Extend tile_slice ComplexPattern to match default case. · ab721827
  Sander de Smalen authored Jun 28, 2022
  ab721827
- [RISCV] Support VECTOR_REVERSE mask operation. · 96ab0836
  Lian Wang authored Jun 27, 2022
  96ab0836
- [RISCV] Optimize 2x SELECT for floating-point types · 1178992c
  LiaoChunyu authored Jun 16, 2022
  1178992c
- [RISCV] Fix misleading formatting and remove a dead getNode call. NFC · ea1b8612
  Craig Topper authored Jun 27, 2022
  
  ea1b8612
Jun 27, 2022
- [RISCV] Remove repeated calls to getSExtValue. NFC · 87077c7e
  Craig Topper authored Jun 27, 2022
  
  87077c7e
- [RISCV] Remove a use of getMinVLen in favor of getRealMinVLen · 0533b6e2
  Philip Reames authored Jun 27, 2022
  0533b6e2
- [RISCV] Cost model for scalable reductions · aadc9d26
  Philip Reames authored Jun 26, 2022
  aadc9d26
- [AMDGPU] Cluster stores as well as loads for GFX11 · b5818e4e
  Jay Foad authored Jun 24, 2022
  b5818e4e
- [SPARC] Don't do leaf optimization on procedures with inline assembly · 1466d65d
  Koakuma authored Jun 27, 2022
  1466d65d
- [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records · 70a5c525
  Lucas Prates authored May 06, 2022
  70a5c525
- ARM: don't try to load function pointer before long call. · 69ae441e
  Tim Northover authored Jun 27, 2022
  69ae441e
- [IR] Move vector.insert/vector.extract out of experimental namespace · a83aa33d
  Bradley Smith authored Jun 16, 2022
  a83aa33d
- [X86] combineConcatVectorOps - IsConcatFree must check extraction index · 0b998053
  Simon Pilgrim authored Jun 27, 2022
  0b998053