Commits · ddbc728828c70728473b47c9f7427aa9514f3d17 · Roger Ferrer / llvm-epi · GitLab

Jan 22, 2020
- [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst. · ddbc7288
  Hiroshi Yamauchi authored Jan 21, 2020
  ddbc7288
- [AArch64] Add test for DWARF return address signing · a8ff6c0b
  Pablo Barrio authored Jan 16, 2020
  a8ff6c0b
- AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop · bb562d1a
  Matt Arsenault authored Jan 04, 2020
  bb562d1a
- [RISCV] Support ABI checking with per function target-features · 0cb274de
  Zakk Chen authored Nov 28, 2019
  0cb274de
- [X86][SSE] combineExtractWithShuffle - extract(bictcast(scalar_to_vector(x))) --> x · a14aa7da
  Simon Pilgrim authored Jan 22, 2020
  a14aa7da
- AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT · 52ec7379
  Matt Arsenault authored Jan 03, 2020
  52ec7379
- AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT · d1dbb5e4
  Matt Arsenault authored Jan 03, 2020
  
  d1dbb5e4
- AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT · 3524d441
  Matt Arsenault authored Jan 03, 2020
  3524d441
- AMDGPU/GlobalISel: Fold constant offset vector extract indexes · e3d352c5
  Matt Arsenault authored Jan 03, 2020
  e3d352c5
- [VE] select and selectcc patterns · 83b67526
  Kazushi (Jam) Marukawa authored Jan 22, 2020
  83b67526
- AMDGPU: Look through casted selects to constant fold bin ops · 2fe500ab
  Matt Arsenault authored Jan 20, 2020
  2fe500ab
- AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare · bcd91778
  Matt Arsenault authored Jan 19, 2020
  bcd91778
- AMDGPU/GlobalISel: Add pre-legalize combiner pass · a174f0da
  Matt Arsenault authored Jan 05, 2020
  a174f0da
- [VE] setcc isel patterns · dc69265e
  Kazushi (Jam) Marukawa authored Jan 22, 2020
  dc69265e
- [AArch64][SVE] Add patterns for unpredicated load/store to frame-indices. · 4cf16efe
  Sander de Smalen authored Jan 22, 2020
  4cf16efe
- AMDGPU/GlobalISel: Fix RegbankSelect for llvm.amdgcn.fmul.legacy · 70096ca1
  Matt Arsenault authored Jan 21, 2020
  
  70096ca1
- AMDGPU/GlobalISel: Handle atomic_inc/atomic_dec · a722cbf7
  Matt Arsenault authored Jan 17, 2020
  a722cbf7
- AMDGPU: Fix interaction of tfe and d16 · 9c928649
  Matt Arsenault authored Jan 17, 2020
  9c928649
- AMDGPU/GlobalISel: RegBankSelect interp intrinsics · b94d3b9b
  Matt Arsenault authored Jul 16, 2019
  b94d3b9b
- [AArch64][SVE] Add intrinsic for non-faulting loads · cdcc4f2a
  Kerry McLaughlin authored Jan 22, 2020
  cdcc4f2a
- Add support for (expressing) vscale. · 67d4c992
  Sander de Smalen authored Jan 21, 2020
  67d4c992
- [ARM][MVE] Clear MaskedInsts vector · c04b9ba5
  Sam Parker authored Jan 22, 2020
  c04b9ba5
- [VE] i<N> and fp32/64 arguments, return values and constants · 3a906a9f
  Kazushi (Jam) Marukawa authored Jan 22, 2020
  3a906a9f
- [AArch64][GlobalISel] Fix llvm.returnaddress(0) selection when LR is clobbered. · 2e25d75a
  Amara Emerson authored Jan 21, 2020
  2e25d75a
- [AMDGPU] SIRemoveShortExecBranches should not remove branches exiting loops · 6b4b3e28
  Carl Ritson authored Jan 22, 2020
  6b4b3e28
- Resubmit: [AMDGPU] Invert the handling of skip insertion. · e53a9d96
  cdevadas authored Jan 22, 2020
  e53a9d96
- [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible. · 67a87753
  Amara Emerson authored Jan 17, 2020
  67a87753
Jan 21, 2020
- [AArch64] Add custom store lowering for 256 bit non-temporal stores. · 535ed62c
  Florian Hahn authored Jan 21, 2020
  535ed62c
- AMDGPU/GlobalISel: Legalize G_PTR_ADD for arbitrary pointers · fd109308
  Matt Arsenault authored Jan 21, 2020
  fd109308
- [Hexagon] Add REQUIRES: asserts to a testcase using -debug-only · 6cf95ac2
  Krzysztof Parzyszek authored Jan 21, 2020
  
  6cf95ac2
- [WebAssembly][InstrEmitter] Foundation for multivalue call lowering · 3ef169e5
  Thomas Lively authored Dec 13, 2019
  3ef169e5
- [PowerPC] Delete PPCSubtarget::isDarwin and isDarwinABI · 8e1f0974
  Fangrui Song authored Jan 01, 2020
  8e1f0974
- [StackColoring] Remap PseudoSourceValue frame indices via MachineFunction::getPSVManager() · 7a8b0b15
  Fangrui Song authored Jan 20, 2020
  7a8b0b15
- [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) · 305bf5b2
  Krzysztof Parzyszek authored Jan 13, 2020
  
  305bf5b2
- Update spelling of {analyze,insert,remove}Branch in strings and comments · 020041d9
  Krzysztof Parzyszek authored Jan 21, 2020
  020041d9
- [RISCV] Check the target-abi module flag matches the option · 1256d680
  Zakk Chen authored Jan 15, 2020
  1256d680
- [TargetLowering] SimplifyDemandedBits ISD::SRA multi-use handling · f04284cf
  Simon Pilgrim authored Jan 21, 2020
  f04284cf
- [TargetLowering] SimplifyDemandedBits ANY_EXTEND/ANY_EXTEND_VECTOR_INREG multi-use handling · 651fa669
  Simon Pilgrim authored Jan 21, 2020
  651fa669
- AMDGPU/GlobalISel: Add some baseline tests for unmerge legalization · 5181c67f
  Matt Arsenault authored Jan 21, 2020
  
  5181c67f
- [DAG] Fold extract_vector_elt (scalar_to_vector), K to undef (K != 0) · 5f5f4785
  Simon Pilgrim authored Jan 21, 2020
  5f5f4785