Commits · ddcba562819969b8fdbf60fd52dc92cfb0df0f0e · Roger Ferrer / llvm-epi · GitLab

Jul 03, 2013
- SystemZInstrInfo.cpp: Tweak an assertion. [-Wunused-variable] · ddcba562
  NAKAMURA Takumi authored Jul 03, 2013
  ddcba562
Jul 02, 2013
- · 42a09dc1
  Ulrich Weigand authored Jul 02, 2013
  42a09dc1
- · 5143bab2
  Ulrich Weigand authored Jul 02, 2013
  5143bab2
- · 40509956
  Ulrich Weigand authored Jul 02, 2013
  40509956
- SystemZ: Fold variable into assertion. · 421c8fb2
  Benjamin Kramer authored Jul 02, 2013
  421c8fb2
- · 0f039824
  Ulrich Weigand authored Jul 02, 2013
  0f039824
- · 2b6fc8d6
  Ulrich Weigand authored Jul 02, 2013
  2b6fc8d6
- Hexagon: Avoid unused variable warnings in Release builds. · 755bf4f6
  Benjamin Kramer authored Jul 02, 2013
  755bf4f6
- Remove address spaces from MC. · 64e1af8e
  Rafael Espindola authored Jul 02, 2013
  64e1af8e
- [SystemZ] Use DSGFR over DSGR in more cases · e6e78855
  Richard Sandiford authored Jul 02, 2013
  e6e78855
- [SystemZ] Use MVC to spill loads and stores · f6bae1e4
  Richard Sandiford authored Jul 02, 2013
  f6bae1e4
- [SystemZ] Add the MVC instruction · 1d959008
  Richard Sandiford authored Jul 02, 2013
  1d959008
- [XCore] Fix instruction selection for zext, mkmsk instructions. · e4cc9868
  Richard Osborne authored Jul 02, 2013
  e4cc9868
- Fix ARM EHABI compact model 1 and 2 without handlerdata. · c931fce4
  Logan Chien authored Jul 02, 2013
  c931fce4
- Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling · 52727c6b
  Hal Finkel authored Jul 02, 2013
  52727c6b
- [mips] Add new InstrItinClasses for move from/to coprocessor instructions and · b34ad786
  Akira Hatanaka authored Jul 02, 2013
  b34ad786
- · f11efe7f
  Ulrich Weigand authored Jul 01, 2013
  f11efe7f
- Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ... · fab01e5c
  Richard Trieu authored Jul 01, 2013
  fab01e5c
Jul 01, 2013
- PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation · 1b01ae86
  David Blaikie authored Jul 01, 2013
  1b01ae86
- · 85c6f7f7
  Ulrich Weigand authored Jul 01, 2013
  85c6f7f7
- Add a newline. · 797ee3e3
  Chad Rosier authored Jul 01, 2013
  797ee3e3
- Index: test/CodeGen/PowerPC/reloc-align.ll · 48fc20a0
  Bill Schmidt authored Jul 01, 2013
  48fc20a0
- [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the · fa705ee3
  Chad Rosier authored Jul 01, 2013
  fa705ee3
- [mips] Reverse the order of source operands of shift and rotate instructions that · 1af66c9b
  Akira Hatanaka authored Jul 01, 2013
  1af66c9b
- · f7152a85
  Ulrich Weigand authored Jul 01, 2013
  f7152a85
- [mips] Increase the number of floating point control registers available to 32. · 263c6af8
  Akira Hatanaka authored Jul 01, 2013
  263c6af8
- Add jump tables handling for MSP430. · 82bedb1f
  Anton Korobeynikov authored Jul 01, 2013
  82bedb1f
- Don't form PPC CTR loops for over-sized exit counts · 25e4a0d4
  Hal Finkel authored Jul 01, 2013
  25e4a0d4
- AArch64: correct CodeGen of MOVZ/MOVK combinations. · 8625fd8c
  Tim Northover authored Jul 01, 2013
  8625fd8c
- Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst") · 7f3d9e1f
  Tim Northover authored Jul 01, 2013
  7f3d9e1f
- · 3a75861b
  Ulrich Weigand authored Jul 01, 2013
  3a75861b
- · 7a9fcdf6
  Ulrich Weigand authored Jul 01, 2013
  7a9fcdf6
- · 98fcc7b6
  Ulrich Weigand authored Jul 01, 2013
  98fcc7b6
- · 797f1a3f
  Ulrich Weigand authored Jul 01, 2013
  797f1a3f
- ARM: relax the atomic release barrier to "dmb ishst" · 953abab4
  Tim Northover authored Jul 01, 2013
  953abab4
- [NVPTX] Add support for module-scope inline asm · d2bbdf05
  Justin Holewinski authored Jul 01, 2013
  d2bbdf05
- [NVPTX] We dont use NVBuiltin anymore · 3694f11f
  Justin Holewinski authored Jul 01, 2013
  3694f11f
- [NVPTX] Cut down on physical register defs · 8fab95d5
  Justin Holewinski authored Jul 01, 2013
  8fab95d5
- [NVPTX] 64-bit ADDC/ADDE are not legal · 51cb1349
  Justin Holewinski authored Jul 01, 2013
  51cb1349
- [NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos · dff28d21
  Justin Holewinski authored Jul 01, 2013
  dff28d21