Commits · de6d640f6d21d78344b6a834f03148963b8a6f5c · Roger Ferrer / llvm-epi · GitLab

Feb 19, 2021
- [RISCV] Remove redundant test cases for index segment store (5/8). · de6d640f
  Hsiangkai Wang authored Feb 19, 2021
  de6d640f
- [RISCV] Remove redundant test cases for index segment load (4/8). · 3b4b1c84
  Hsiangkai Wang authored Feb 19, 2021
  
  3b4b1c84
- [RISCV] Remove redundant test cases for index segment load (3/8). · 8cc0b1cb
  Hsiangkai Wang authored Feb 19, 2021
  8cc0b1cb
- [RISCV] Remove redundant test cases for index segment load (2/8). · 320250e4
  Hsiangkai Wang authored Feb 19, 2021
  
  320250e4
- [RISCV] Remove redundant test cases for index segment load (1/8). · a32c79ce
  Hsiangkai Wang authored Feb 19, 2021
  a32c79ce
- [Coroutine] Relax CoroElide musttail check · 3bf8f162
  Xun Li authored Feb 18, 2021
  3bf8f162
- Reset the EntryValue location flag in finalizeEntryValue. · c4ad878a
  Adrian Prantl authored Feb 18, 2021
  c4ad878a
- [SampleFDO] Stop repeated indirect call promotion for the same target. · 5fb65c02
  Wei Mi authored Feb 12, 2021
  5fb65c02
- MIR: Fix parser crash on syntax error on first character · 2d3d2e78
  Matt Arsenault authored Feb 18, 2021
  2d3d2e78
- [dfsan] Instrument origin variable and function definitions · 7e658b2f
  Jianzhou Zhao authored Feb 18, 2021
  7e658b2f
- [llvm][IR] Do not place constants with static relocations in a mergeable section · c77659e5
  Leonard Chan authored Feb 10, 2021
  c77659e5
Feb 18, 2021
- AMDGPU: Add regression testcase for bundle pressure issue · 27093f1a
  Matt Arsenault authored Feb 03, 2021
  27093f1a
- [Coverage] Store compilation dir separately in coverage mapping · 5fbd1a33
  Petr Hosek authored Feb 10, 2021
  5fbd1a33
- GlobalISel: Merge some AMDGPU ABI lowering code to generic code · 62d946e1
  Matt Arsenault authored Feb 07, 2021
  62d946e1
- [BasicAA] Always strip single-argument phi nodes · 70e3c9a8
  Nikita Popov authored Feb 14, 2021
  70e3c9a8
- [DAGCombiner] Transform (zext (select c, load1, load2)) -> (select c, zextload1, zextload2) · 66f2d09e
  Guozhi Wei authored Feb 18, 2021
  66f2d09e
- [DCE] Add tests for non-willreturn function being removed (NFC) · 4045ad6b
  Nikita Popov authored Feb 18, 2021
  
  4045ad6b
- Revert "[Coverage] Store compilation dir separately in coverage mapping" · fbf8b957
  Petr Hosek authored Feb 18, 2021
  fbf8b957
- Remove redundent types in pr49185.ll · 0c087a6c
  Ta-Wei Tu authored Feb 19, 2021
  
  0c087a6c
- [Coverage] Store compilation dir separately in coverage mapping · 97ec8fa5
  Petr Hosek authored Feb 10, 2021
  97ec8fa5
- [WebAssembly] Fix assert in lookup of section symbols · 508aa69e
  Wouter van Oortmerssen authored Feb 10, 2021
  508aa69e
- [RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. · 8860f190
  Craig Topper authored Feb 18, 2021
  8860f190
- Pre-commit test case · 2cc76b17
  Guozhi Wei authored Feb 18, 2021
  2cc76b17
- [NPM] Properly reset parent loop after loop passes · f70cdc5b
  Ta-Wei Tu authored Feb 19, 2021
  f70cdc5b
- [PowerPC][AIX] Add support for vector arg passing on the stack. · bb260b1c
  Sean Fertile authored Feb 18, 2021
  bb260b1c
- [WebAssembly] Handle multiple EH_LABELs in EH pad · 6f2999b3
  Heejin Ahn authored Feb 18, 2021
  6f2999b3
- [RISCV] Pre-commit test file changes from D96661. NFC · c9d56df2
  Craig Topper authored Feb 18, 2021
  c9d56df2
- [RISCV] Add support for fixed vector MULHU/MULHS. · 156fc07e
  Craig Topper authored Feb 18, 2021
  156fc07e
- [RISCV] Add support for fixed vector sign/zero extend from mask types. · 792627be
  Craig Topper authored Feb 18, 2021
  792627be
- [RISCV] Support isel of scalable vector bitcasts · c7dd92e8
  Craig Topper authored Feb 18, 2021
  c7dd92e8
- AMDGPU: Fix checks in llvm.amdgcn.workitem.id.ll · 622652bf
  Konstantin Zhuravlyov authored Feb 18, 2021
  622652bf
- [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD · 8bad8a43
  Bradley Smith authored Feb 08, 2021
  8bad8a43
- [TableGen][SelectionDAG] Improve efficiency of encoding negative immediates... · 61d4d9a5
  Craig Topper authored Feb 18, 2021
  61d4d9a5
- [AArch64] Allow folding FMUL/FADD into FMA for FP16 types · 5b094bfe
  Bradley Smith authored Feb 12, 2021
  5b094bfe
- [instcombine] Exploit UB implied by nofree attributes · 86664638
  Philip Reames authored Feb 18, 2021
  86664638
- [Verifier] add tests for vector reductions; NFC · a1e5388a
  Sanjay Patel authored Feb 18, 2021
  a1e5388a
- [ARM] Expand the range of allowed post-incs in load/store optimizer · 3b34b06f
  David Green authored Feb 18, 2021
  3b34b06f
- [AMDGPU] Tidy up a FIXME fixed by D34973 · e1b1119f
  Jay Foad authored Feb 18, 2021
  
  e1b1119f
- Revert "[TableGen] Improve algorithms for processing template arguments" · 49d663d5
  Paul C. Anagnostopoulos authored Feb 18, 2021
  49d663d5
- [PowerPC] Exploit the vinsw, vinsd, and vins[wd][lr]x instructions on P10 · 34dc1ccb
  Baptiste Saleil authored Feb 17, 2021
  34dc1ccb