Commits · deda60fcaf0be162e893ff68d8d91355e3ac5542 · Roger Ferrer / llvm-epi · GitLab

Apr 22, 2021
- [Hexagon] Add HVX intrinsics for conditional vector loads/stores · deda60fc
  Krzysztof Parzyszek authored Apr 22, 2021
  deda60fc
- [x86] remove stale comment from test file; NFC · 11232037
  Sanjay Patel authored Apr 22, 2021
  
  11232037
- [Hexagon] Unmasked and masked load pair to dame bae -? one load and selects · f3451162
  Coplin, Jared authored Apr 22, 2021
  
  f3451162
- [AArch64] Block tryCombineToBSL combines for vectors wider than NEON · 528ee161
  Joe Ellis authored Apr 22, 2021
  528ee161
- Revert "[Hexagon] Masked and unmasked load to same base -> load and two selects" · e8d04754
  Krzysztof Parzyszek authored Apr 22, 2021
  e8d04754
- AArch64: support mixed-size fp <-> int conversions in GlobalISel. · 2e72f6b5
  Tim Northover authored Apr 20, 2021
  
  2e72f6b5
- AArch64: expand G_DIVREM operations in GlobalISel · ac1647cc
  Tim Northover authored Apr 20, 2021
  ac1647cc
- [Hexagon] Masked and unmasked load to same base -> load and two selects · 96dc8d7e
  Coplin, Jared authored Apr 22, 2021
  
  96dc8d7e
- [X86] Regenerate atomic-eflags-reuse.ll · 05953cf6
  Simon Pilgrim authored Apr 22, 2021
  
  05953cf6
- [DAGCombiner] Allow operand of step_vector to be negative. · 978eb3f1
  Jun Ma authored Apr 19, 2021
  978eb3f1
- [X86][AVX] Add PR49971 test case · e28ae5e5
  Simon Pilgrim authored Apr 22, 2021
  e28ae5e5
- [PowerPC] Improve codegen for vector fp to int widening conversions · 092619cf
  Nemanja Ivanovic authored Apr 21, 2021
  092619cf
- [AArch64] Fix calling windows varargs with floats in fixed args from non-windows functions · 8000e1f5
  Martin Storsjö authored Apr 21, 2021
  8000e1f5
- [RISCV] Custom lowering of SET_ROUNDING · 740962e5
  Serge Pavlov authored Nov 10, 2020
  740962e5
- [CodeGen] Do not split functions with attr "implicit-section-name". · 8077d0ff
  Snehasish Kumar authored Apr 21, 2021
  8077d0ff
- [RISCV] Custom lowering of FLT_ROUNDS_ · 6e63dfda
  Serge Pavlov authored Nov 05, 2020
  6e63dfda
- [RISCV] Teach lowerSPLAT_VECTOR_PARTS to detect cases where Hi is sign extended from Lo. · f6d8cf77
  Craig Topper authored Apr 21, 2021
  f6d8cf77
- AMDGPU: Fix assert when trying to fold reg_sequence of physreg copies · 987e5285
  Matt Arsenault authored Apr 20, 2021
  
  987e5285
- Delete le32/le64 targets · 77ac823f
  Fangrui Song authored Apr 21, 2021
  77ac823f
- [AArch64][GlobalISel] Fix regbankselect for G_FCMP with vector destinations · 3011aa1a
  Jessica Paquette authored Apr 20, 2021
  3011aa1a
- [AArch64][GlobalISel] Mark some vector G_ABS cases as legal · 6cb75990
  Jessica Paquette authored Apr 20, 2021
  6cb75990
Apr 21, 2021
- [MC] Use COMDAT for LSDA only if IR comdat type is any · 7a718e16
  Petr Hosek authored Apr 20, 2021
  7a718e16
- [X86][SSE] getFauxShuffleMask - don't decode OR(SHUFFLE,SHUFFLE) containing UNDEFs. (PR50049) · a511b55c
  Simon Pilgrim authored Apr 21, 2021
  a511b55c
- [AArch64][SVE] Fix crash with icmp+select · ca9b7e2e
  Caroline Concatto authored Apr 12, 2021
  ca9b7e2e
- AMDGPU: Fix indirect tail calls · 70ab76a8
  Matt Arsenault authored Apr 20, 2021
  70ab76a8
- [AArch64] Add and update reverse mask tests. NFC · c6e2aedb
  David Green authored Apr 21, 2021
  
  c6e2aedb
- [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines · c141bd3c
  Fraser Cormack authored Apr 20, 2021
  c141bd3c
- [RISCV] Further fixes for RVV stack offset computation · 3f02d269
  Fraser Cormack authored Apr 20, 2021
  3f02d269
- [RISCV] Add missing SEW=64 tests to vmslt-rv32.ll. NFC · 78abad56
  Craig Topper authored Apr 20, 2021
  
  78abad56
- Make sure PHIElimination doesn't copy debug locations across basic blocks. · 81cad0be
  Adrian Prantl authored Apr 20, 2021
  81cad0be
Apr 20, 2021
- [WebAssembly] More codegen for f64x2.convert_low_i32x4_{s,u} · 693d767c
  Thomas Lively authored Apr 20, 2021
  693d767c
- [X86][SSE] combineX86ShuffleChain - check if we're blending with zero into already zero elements · 2a419a0b
  Simon Pilgrim authored Apr 20, 2021
  2a419a0b
- [AMDGPU] Allow multiple uses of the same literal · ec8c61ef
  Jay Foad authored Apr 08, 2021
  ec8c61ef
- [ARM] Limit PerformExtractEltToVMOVRRD to when f64 is legal. · 21a8b9d9
  David Green authored Apr 20, 2021
  21a8b9d9
- AMDGPU/GlobalISel: Fix uitofp/sitofp with non-power-of-2 integers · 1cb8a9d5
  Matt Arsenault authored Mar 27, 2021
  
  1cb8a9d5
- GlobalISel: Restrict narrow scalar for fptoui/fptosi results · 83a25a10
  Matt Arsenault authored Mar 26, 2021
  83a25a10
- [AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions · b8b075d8
  Bradley Smith authored Apr 13, 2021
  b8b075d8
- [ARM] Create VMOVRRD from adjacent vector extracts · 48cef1fa
  David Green authored Apr 20, 2021
  48cef1fa
- [RISCV][NFC] Add tests for scalable-vector DAGCombiner improvements · 60622b82
  Fraser Cormack authored Apr 20, 2021
  60622b82
- [PowerPC] Canonicalize shuffles on big endian targets as well · 03e7feff
  Nemanja Ivanovic authored Apr 20, 2021
  03e7feff