Commits · def7cfb7ffd40691f903287a060f4405bab56d1a · Roger Ferrer / llvm-epi · GitLab

Nov 22, 2020
- [InstCombine] Use is_contained (NFC) · def7cfb7
  Kazu Hirata authored Nov 21, 2020
  
  def7cfb7
Nov 21, 2020
- Fix shared build. · dcc06597
  Michael Liao authored Nov 21, 2020
  
  dcc06597
- [BasicAA] Remove unnecessary sextOrSelf (NFC) · ded59288
  Nikita Popov authored Nov 21, 2020
  ded59288
- [BasicAA] Return DecomposedGEP (NFC) · 0d114f56
  Nikita Popov authored Nov 21, 2020
  0d114f56
- [BasicAA] Remove some intermediate variables (NFC) · f4412c5a
  Nikita Popov authored Nov 21, 2020
  f4412c5a
- [BasicAA] Remove stale FIXME (NFC) · 913a99c4
  Nikita Popov authored Nov 21, 2020
  913a99c4
- [X86] Include %rip for 32-bit RIP-relative relocs for x32 · 4629afa1
  Harald van Dijk authored Nov 21, 2020
  4629afa1
- MachineDominators.h - remove unused <vector> include · 5318f6c4
  Simon Pilgrim authored Nov 21, 2020
  
  5318f6c4
- DominanceFrontier - remove unused <vector> includes · 7650d655
  Simon Pilgrim authored Nov 21, 2020
  
  7650d655
- [X86] Regenerate vector-reduce-or-cmp.ll · 63626a19
  Simon Pilgrim authored Nov 21, 2020
  63626a19
- [Flang][OpenMP][NFC][2/2] Reorder OmpStructureChecker and simplify it. · 1df8fa78
  sameeran joshi authored Nov 05, 2020
  1df8fa78
- [BasicAA] Add recphi test with dynamic offset (NFC) · 072ddff3
  Nikita Popov authored Nov 21, 2020
  072ddff3
- [TableGen] [ISel Matcher Emitter] Rework with two passes: one to size, one to emit · 9b7b8de6
  Paul C. Anagnostopoulos authored Nov 16, 2020
  9b7b8de6
- [flang][openmp] Fix bug in `OmpClause::Hint` clause which was missing to... · 42ecf188
  sameeran joshi authored Nov 21, 2020
  42ecf188
- [VE][NFC] Modify function order and simplify comments · 4a1d230f
  Kazushi (Jam) Marukawa authored Nov 19, 2020
  
  4a1d230f
- [VE] Correct types of return/argument values for getAdjustedFrameSize() · 02b2bcd9
  Kazushi (Jam) Marukawa authored Nov 15, 2020
  02b2bcd9
- [NFC][AMDGPU] Document kernel descriptor · 8605d313
  Tony authored Nov 13, 2020
  8605d313
- [VE][NFC] Update missing bulk update tests to use typed sret · a2dc4ac8
  Kazushi (Jam) Marukawa authored Nov 21, 2020
  
  a2dc4ac8
- OpaquePtr: Make byval/sret types mandatory · 41083267
  Matt Arsenault authored Nov 20, 2020
  
  41083267
- AMDGPU: Fix counting kernel arguments towards register usage · 79f75468
  Matt Arsenault authored Oct 20, 2020
  79f75468
- [Analysis] Use llvm::is_contained (NFC) · 226beb49
  Kazu Hirata authored Nov 20, 2020
  
  226beb49
- Verifier: Fix assert when verifying non-pointer byval or preallocated · 650fbd56
  Matt Arsenault authored Nov 20, 2020
  650fbd56
- OpaquePtr: Update more tests to use typed sret · 1d1234b2
  Matt Arsenault authored Nov 20, 2020
  
  1d1234b2
- [llvm-profgen][NFC]Fix build failure on different platform · 21c91454
  wlei authored Nov 20, 2020
  21c91454
Nov 20, 2020
- OpaquePtr: Bulk update tests to use typed sret · 20c43d6b
  Matt Arsenault authored Nov 20, 2020
  
  20c43d6b
- [CSSPGO][llvm-profgen] Instruction symbolization · 0196b45c
  wlei authored Oct 19, 2020
  0196b45c
- [CSSPGO][llvm-profgen] Disassemble text sections · 32221694
  wlei authored Oct 19, 2020
  32221694
- [CSSPGO][llvm-profgen] Parse mmap events from perf script · a94fa862
  wlei authored Oct 18, 2020
  a94fa862
- [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. · c58df888
  Amara Emerson authored Nov 20, 2020
  c58df888
- Demangling support for class type non-type template parameter extensions. · bec968cb
  Richard Smith authored Oct 22, 2020
  bec968cb
- [SLP][NFC]Fix assert condition in newTreeEntry, NFC. · 0b420d67
  Alexey Bataev authored Nov 20, 2020
  
  0b420d67
- [RISCV] Put RV32 before RV64 in the ValueTypeByHwMode and RegInfoByHwMode... · 9211da42
  Craig Topper authored Nov 20, 2020
  9211da42
- [RISCV] Remove RV32 HwMode. Use DefaultMode for RV32 · 77e25b5b
  Craig Topper authored Nov 20, 2020
  77e25b5b
- OpaquePtr: Bulk update tests to use typed byval · 06c192d4
  Matt Arsenault authored Nov 20, 2020
  06c192d4
- [CSSPGO] MIR target-independent pseudo instruction for pseudo-probe intrinsic · d0e42037
  Hongtao Yu authored Sep 10, 2020
  d0e42037
- [RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension · 6a1d8b91
  Craig Topper authored Nov 20, 2020
  6a1d8b91
- [CSSPGO] IR intrinsic for pseudo-probe block instrumentation · f3c44569
  Hongtao Yu authored Nov 18, 2020
  f3c44569
- [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb. · 78767b7f
  Craig Topper authored Nov 20, 2020
  78767b7f
- [X86][AVX] LowerADDSAT_SUBSAT - avoid X86ISD::BLENDV in UADDSAT/USUBSAT v8i32/v4i64 lowering · 0341029b
  Simon Pilgrim authored Nov 20, 2020
  0341029b
- [SelectionDAG][X86][PowerPC][Mips] Replace the default implementation of... · a7eae62a
  Craig Topper authored Nov 20, 2020
  a7eae62a