llvm-svn: 154834

llvm-svn: 154833

llvm-svn: 154830

through the use of 'fpmath' metadata.  Currently this only provides a 'fpaccuracy'
value, which may be a number in ULPs or the keyword 'fast', however the intent is
that this will be extended with additional information about NaN's, infinities
etc later.  No optimizations have been hooked up to this so far.

llvm-svn: 154822

llvm-svn: 154796

llvm-svn: 154788

llvm-svn: 154766

llvm-svn: 154755

by Sundeep Kushwaha.

llvm-svn: 154754

llvm-svn: 154752

llvm-svn: 154692

llvm-svn: 154590

Cygwin-1.7 supports dw2. Some recent mingw distros support one, too.
I have confirmed test-suite/SingleSource/Benchmarks/Shootout-C++/except.cpp can pass on Cygwin.

llvm-svn: 154247

llvm-svn: 153508

Thanks Duncan.

llvm-svn: 153411

llvm-svn: 153391

llvm-svn: 153296

llvm-svn: 153224

Add a random .LL file generator to stress-test different llvm components.

llvm-svn: 151479

llvm-svn: 151308

llvm-svn: 150712

llvm-svn: 150677

llvm-svn: 149972

llvm-svn: 149914

Register masks will be used as a compact representation of large clobber
lists.  Currently, an x86 call instruction has some 40 operands
representing call-clobbered registers.  That's more than 1kB of useless
operands per call site.

A register mask operand references a bit mask of call-preserved
registers, everything else is clobbered.  The bit mask will typically
come from TargetRegisterInfo::getCallPreservedMask().

By abandoning ImplicitDefs for call-clobbered registers, it also becomes
possible to share call instruction descriptions between calling
conventions, and we can get rid of the WINCALL* instructions.

This patch introduces the new operand kind.  Future patches will add
RegMask support to target-independent passes before finally the fixed
clobber lists can be removed from call instruction descriptions.

llvm-svn: 148250

The register allocators don't currently support adding reserved
registers while they are running.  Extend the MRI API to keep track of
the set of reserved registers when register allocation started.

Target hooks like hasFP() and needsStackRealignment() can look at this
set to avoid reserving more registers during register allocation.

llvm-svn: 147577

1. pointer-vector
2. type legalizer changes and vector-select
3. X86 ISA changes.

llvm-svn: 146964

llvm-svn: 146939

Add the new TableGen register class synthesizer feature to the release
notes.

llvm-svn: 146875

The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

llvm-svn: 146739

llvm-svn: 146603

llvm-svn: 146505

llvm-svn: 146493

llvm-svn: 145991

llvm-svn: 145979

llvm-svn: 145964

llvm-svn: 145590

llvm-svn: 145518

-fplugin-arg-dragonegg-enable-gcc-optzns, though it usually isn't
a win.

llvm-svn: 145486

llvm-svn: 145419