Commits · dfeea84d63f737ddded2531c8c309a7f93fecf38 · Roger Ferrer / llvm-epi · GitLab

Mar 23, 2018
- [X86] Give VPCMPEQQ the same itinerary as its SSE counterpart. · dfeea84d
  Craig Topper authored Mar 23, 2018
  dfeea84d
- [X86] Correct the latencies of SNB integer vector multiplies based on Agner's... · 4787b7f4
  Craig Topper authored Mar 23, 2018
  4787b7f4
- [X86] Match vpblendvb/vblendvps/vblendvpd itineraries to the SSE equivalent.... · 659c66df
  Craig Topper authored Mar 23, 2018
  659c66df
- [X86] Change VPSADBW itinerary to SSE_INTALU_ITINS_P to match the SSE version. · 7580a799
  Craig Topper authored Mar 23, 2018
  7580a799
- [X86] Give VLDDQUrm and LDDQUrm the same itinerary. · d5ac3ae8
  Craig Topper authored Mar 23, 2018
  d5ac3ae8
- [X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model. · 7f142b8b
  Craig Topper authored Mar 23, 2018
  7f142b8b
- [X86] Add VEXTRB/W/D/Q to Zen scheduler model. · fae4173b
  Craig Topper authored Mar 23, 2018
  fae4173b
- [X86] Fix the itinerary for vextractps to match extractps. · 6ef55d18
  Craig Topper authored Mar 23, 2018
  6ef55d18
- [DAG] Fix node id invalidation in Instruction Selection. · 5b3e8791
  Nirav Dave authored Mar 23, 2018
  5b3e8791
- [TableGen] Don't capture returned std::vectors by const reference. · 37eeb320
  Craig Topper authored Mar 23, 2018
  37eeb320
- For llvm-nm and Mach-O files also use function starts info in some · d3cf76ba
  Kevin Enderby authored Mar 22, 2018
  d3cf76ba
- State that CFG is preserved in 'Falkor HW Prefetch Fix Late Phase'. · fab7a676
  Michael Zolotukhin authored Mar 22, 2018
  fab7a676
- [Support/Parallel] Use lock_guard which has less overhead than unique_lock. · 41e8e529
  Fangrui Song authored Mar 22, 2018
  41e8e529
- Reapply "[test] Add tests for llc passes pipelines." with a fix for bots with expensive checks on. · 3520331f
  Michael Zolotukhin authored Mar 22, 2018
  3520331f
Mar 22, 2018
- Move SampleProfile.h into IPO along with the rest of the IPO pass headers · 301627f8
  David Blaikie authored Mar 22, 2018
  301627f8
- [X86] Correct the VROUND regular expressions in Znver1 scheduler model to account for r328254 · adb17331
  Craig Topper authored Mar 22, 2018
  adb17331
- Finish moving the IPSCCP pass from Scalar to IPO - moving the registration · 376294c2
  David Blaikie authored Mar 22, 2018
  376294c2
- Revert r325687 (workaround for PR36032). · 579507a5
  Evgeny Stupachenko authored Mar 22, 2018
  579507a5
- Add test for demangling GNU ABI tags. · 56d4846f
  Rafael Espindola authored Mar 22, 2018
  56d4846f
- [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and... · 40d3b32e
  Craig Topper authored Mar 22, 2018
  40d3b32e
- [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst)) · 17ff975e
  Guozhi Wei authored Mar 22, 2018
  17ff975e
- Fix layering between SCCP and IPO SCCP · 3bbf5af0
  David Blaikie authored Mar 22, 2018
  3bbf5af0
- [MIR] Making MIR Printing, opt -dot-cfg, and -debug printing faster · d96de6f6
  Roman Tereshin authored Mar 22, 2018
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- Revert "Revert "[InstrProf] Support for external functions in text format."" · 29a21bab
  Mircea Trofin authored Mar 22, 2018
  29a21bab
- [X86][SkylakeClient] Fix a bunch of instructions that were incorrectly... · 58afb4ea
  Craig Topper authored Mar 22, 2018
  58afb4ea
- [MachineOutliner][NFC] Refactoring + comments in runOnModule · df82274f
  Jessica Paquette authored Mar 22, 2018
  df82274f
- [CodeGen] Add a new pass for PostRA sink · 2ecb7ba4
  Jun Bum Lim authored Mar 22, 2018
  2ecb7ba4
- Document optforfuzzing attribute created in r328214. · 3181941b
  Matt Morehouse authored Mar 22, 2018
  3181941b
- [DWARF] Replace assert with diagnostic. PR36868. · 7947468e
  Paul Robinson authored Mar 22, 2018
  7947468e
- Move the initialization of the Meta Renamer pass over to IPO along with the... · 2965a01e
  David Blaikie authored Mar 22, 2018
  2965a01e
- [DAG, X86] Fix ISel-time node insertion ids · 8c5f47ac
  Nirav Dave authored Mar 22, 2018
  8c5f47ac
- [X86] Correct the scheduling data for some of the 32 and 64 bit multiplies to... · 4a3be6e5
  Craig Topper authored Mar 22, 2018
  4a3be6e5
- [InstCombineCalls] Update deprecated API usage (NFC) · 710d7b99
  Daniel Neilson authored Mar 22, 2018
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- [X86][Btver2] Conversion, MaskedLoad/MaskedStore and NTStores all are... · bcb86bb9
  Simon Pilgrim authored Mar 22, 2018
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- [X86][Btver2] FCMP (inc FMAX/FMIN) instructions use the JFPA functional pipe · 0e031afa
  Simon Pilgrim authored Mar 22, 2018
  0e031afa
- [Codeview/PDB] Rename some methods for clarity. · 71d36ad9
  Zachary Turner authored Mar 22, 2018
  71d36ad9
- [GISel]: Fix incorrect IRTranslation while translating null pointer types · b3297ef0
  Aditya Nandakumar authored Mar 22, 2018
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- [X86][Btver2] FMUL ymm instructions are double pumped on the JFPM functional pipe · e5b51f67
  Simon Pilgrim authored Mar 22, 2018
  e5b51f67
- [ARM] Enable the full InstRW overlap check for ARMScheduleR52.td · 7ccb5ebe
  Craig Topper authored Mar 22, 2018
  7ccb5ebe
- [SimplifyCFG] Create attribute for fuzzing-specific optimizations. · 236cdaf8
  Matt Morehouse authored Mar 22, 2018
  236cdaf8