Commits · e1b1119f21cb7718f80c1ba81318a6c288bac2e3 · Roger Ferrer / llvm-epi · GitLab

Feb 18, 2021
- [AMDGPU] Tidy up a FIXME fixed by D34973 · e1b1119f
  Jay Foad authored Feb 18, 2021
  
  e1b1119f
- [PowerPC] Exploit the vinsw, vinsd, and vins[wd][lr]x instructions on P10 · 34dc1ccb
  Baptiste Saleil authored Feb 17, 2021
  34dc1ccb
- [PowerPC] Add option for ROP Protection · b80357d4
  Stefan Pintilie authored Feb 18, 2021
  b80357d4
- [ARM] Add larger than legal ICmp costs · 1a6744e3
  David Green authored Feb 18, 2021
  1a6744e3
- [X86][SSE] Add uniform vector shift test coverage for (sra (trunc (sr[al] x, c1)), c2) folds · 24aa3025
  Simon Pilgrim authored Feb 17, 2021
  
  24aa3025
- [ARM] MVE ICmp costing tests. NFC · 1fbb3287
  David Green authored Feb 18, 2021
  
  1fbb3287
- [RISCV] Begin to support more subvector inserts/extracts · d8762149
  Fraser Cormack authored Feb 17, 2021
  d8762149
- [SVE][CodeGen] Expand SVE MULH[SU] and [SU]MUL_LOHI nodes · 0176fecf
  Fraser Cormack authored Feb 17, 2021
  0176fecf
- [X86] Zero AMX config buffer for non AVX512 cases. · e9c11c19
  Wang, Pengfei authored Feb 18, 2021
  e9c11c19
- [X86] Add AVX2/SSE2 checks for AMX config buffer zeroing. NFC · 9dcfb95b
  Wang, Pengfei authored Feb 18, 2021
  
  9dcfb95b
- [RISCV] Guard LowerINSERT_VECTOR_ELT against fixed vectors. · 016eca8f
  Craig Topper authored Feb 17, 2021
  016eca8f
- [RISCV] Guard the ISD::EXTRACT_VECTOR_ELT handling in ReplaceNodeResults... · 00c4e0a8
  Craig Topper authored Feb 17, 2021
  00c4e0a8
- [AMDGPU] gfx90a support · a8d9d507
  Stanislav Mekhanoshin authored Feb 17, 2021
  a8d9d507
Feb 17, 2021
- [GlobalISel] Implement computeNumSignBits for G_ASSERT_SEXT · 26fb0365
  Jessica Paquette authored Feb 17, 2021
  26fb0365
- [SystemZ] Separate LoZ ELF specifics in tablegen. · 8b624a31
  Yusra Syeda authored Feb 17, 2021
  8b624a31
- [GlobalISel] Add G_ASSERT_SEXT · 60aa6464
  Jessica Paquette authored Feb 17, 2021
  60aa6464
- [WebAssemblly] Fix EHPadStack update in fixCallUnwindMismatches · da01a9db
  Heejin Ahn authored Feb 15, 2021
  da01a9db
- [WebAssembly] Do not use EHCatchret symbols with wasm EH · 1f9e551a
  Derek Schuff authored Feb 16, 2021
  1f9e551a
- [LSR] Add a flag that overrides the target's preferred addressing mode · f78aa8b2
  Sjoerd Meijer authored Feb 17, 2021
  f78aa8b2
- [PowerPC][AIX] Enable Shrinkwrapping on 32 and 64 bit AIX. · cb287680
  Sidharth Baveja authored Feb 17, 2021
  cb287680
- [PowerPC] Handle FP physical register in inline asm constraint. · 4e127bce
  Sean Fertile authored Feb 17, 2021
  4e127bce
- [AMDGPU] Add implicit vcc_lo on S_CBRANCH_VCCNZ in wave32 · c72a63b4
  Piotr Sobczak authored Feb 17, 2021
  c72a63b4
- [DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) (REAPPLIED) · 05c64ea6
  Simon Pilgrim authored Feb 17, 2021
  05c64ea6
- [AMDGPU] Fix a miscompile with S_ADD/S_SUB · 08131c74
  Piotr Sobczak authored Feb 10, 2021
  08131c74
- [RISCV] Add support for fixed vector vselect · d8116164
  Fraser Cormack authored Feb 15, 2021
  d8116164
- [X86][SSE] Add testcase for bug reported in D96345 · f0d8e733
  Simon Pilgrim authored Feb 17, 2021
  f0d8e733
- [MachineSink] Add a loop sink limit · 7f3170ec
  Sjoerd Meijer authored Feb 16, 2021
  7f3170ec
- [RISCV] Spilling for RISC-V V extension. (2nd version) · a3c783db
  Hsiangkai Wang authored Jan 08, 2021
  a3c783db
- [RISCV] Frame handling for RISC-V V extension. · 5a31a673
  Hsiangkai Wang authored Jan 08, 2021
  5a31a673
- [AMDGPU] Correct rmw atomics s_waitcnt generation · c62b737a
  Tony Tye authored Feb 16, 2021
  c62b737a
- Basic block sections should enable function sections implicitly. · d1a838ba
  Sriraman Tallam authored Feb 16, 2021
  d1a838ba
Feb 16, 2021
- [MC][ELF] Support for zero flag section groups · 16af9739
  Petr Hosek authored Jan 31, 2021
  16af9739
- Revert "[DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d)))" · 5aa8f4c0
  Sterling Augustine authored Feb 16, 2021
  5aa8f4c0
- [RISCV] Add isel patterns for fixed vector fmsub/fnmadd/fnmsub. · 61a238e6
  Craig Topper authored Feb 16, 2021
  
  61a238e6
- [RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 · acfab44e
  Craig Topper authored Feb 16, 2021
  acfab44e
- Revert "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" · 962b73dd
  Jessica Paquette authored Feb 16, 2021
  962b73dd
- [DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UADDSAT as clamped add · df45c181
  Simon Pilgrim authored Feb 16, 2021
  df45c181
- [RISCV] Add support for fixed vector mask logic operations. · 07ca13fe
  Craig Topper authored Feb 16, 2021
  07ca13fe
- [SelectionDAG][AArch64] Restrict matchUnaryPredicate to only handle... · 064ada4e
  Craig Topper authored Feb 16, 2021
  064ada4e
- [AArch64] Convert CMP/SELECT sign patterns to OR & ASR. · 211147c5
  Florian Hahn authored Feb 16, 2021
  211147c5