Commits · e2692f0ee7f338fea4fc918669643315cefc7678 · Roger Ferrer / llvm-epi · GitLab

Jul 15, 2020
- [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions · e2692f0e
  lewis-revill authored Jul 15, 2020
  e2692f0e
- [RISCV] Duplicate pseudo expansion comment to RISCVMCCodeEmitter · 2dc16fbd
  Jessica Clarke authored Jul 15, 2020
  2dc16fbd
- [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos · 3382c243
  Jessica Clarke authored Jul 15, 2020
  3382c243
Jul 14, 2020
- [RISCV] Fix isStoreToStackSlot · 0cbdd2a8
  Roger Ferrer authored Jul 14, 2020
  0cbdd2a8
- Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" · 1d15bbb9
  Sam Elliott authored Jul 14, 2020
  1d15bbb9
Jul 13, 2020
- RISCV: Avoid GlobalISel build break in a future patch · db091e12
  Matt Arsenault authored Jul 13, 2020
  db091e12
- [MC][RISCV] Set UseIntegratedAssembler to true · 4d5fd0ee
  Fangrui Song authored Jul 12, 2020
  4d5fd0ee
Jul 10, 2020
- [RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive · 04b9a46c
  Zakk Chen authored Apr 30, 2020
  04b9a46c
Jul 09, 2020
- [RISCV] Avoid Splitting MBB in RISCVExpandPseudo · 97106f9d
  Sam Elliott authored Jul 09, 2020
  97106f9d
Jul 08, 2020
- [RISCV] optimize addition with a pair of (addi imm) · 1e9d0811
  Ben Shi authored Jul 07, 2020
  1e9d0811
- [RISCV] Optimize multiplication by constant · cb82de29
  Ben Shi authored Jul 07, 2020
  cb82de29
Jul 06, 2020
- [RISCV] Fold ADDIs into load/stores with nonzero offsets · 61c2a0bb
  Luís Marques authored Jun 24, 2020
  61c2a0bb
Jul 01, 2020
- [RISCV] Add mcountinhibit CSR · d36f2c6a
  Pengxuan Zheng authored Jun 30, 2020
  d36f2c6a
- [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2 · b2aa546b
  Luís Marques authored Jul 01, 2020
  b2aa546b
- Revert "[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2" · a61fa1a4
  Luís Marques authored Jul 01, 2020
  a61fa1a4
- [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2 · 05a20a9e
  Luís Marques authored Jul 01, 2020
  05a20a9e
- [RISCV] Implement Hooks to avoid chaining SELECT · 7dc89266
  Sam Elliott authored Jul 01, 2020
  7dc89266
- [Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align · 28de229b
  Guillaume Chatelet authored Jul 01, 2020
  28de229b
Jun 30, 2020
- RISCV: Don't store function in RISCVMachineFunctionInfo · 08649f0a
  Matt Arsenault authored Jun 30, 2020
  08649f0a
Jun 29, 2020
- [RISCV] Split the pseudo instruction splitting pass · 2cb0644f
  Luís Marques authored Jun 29, 2020
  2cb0644f
Jun 27, 2020
- [RISCV] Silence unused variable warning in Release builds. NFC. · 85b53598
  Benjamin Kramer authored Jun 27, 2020
  
  85b53598
- [RISCV] Assemble/Disassemble v-ext instructions. · 66da87dc
  Hsiangkai Wang authored Oct 24, 2019
  66da87dc
Jun 25, 2020
- [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign · 2e7bba69
  Guillaume Chatelet authored Jun 25, 2020
  2e7bba69
Jun 18, 2020
- [RISCV64] Emit correct lib call for fp(float/double) to ui/si · 7622ea58
  Kamlesh Kumar authored Jun 18, 2020
  7622ea58
Jun 10, 2020
- [RISCV] Make visibility of overridden methods in RISCVISelLowering match the parent · d9bc8bd5
  Alex Bradbury authored Jun 10, 2020
  d9bc8bd5
Jun 08, 2020
- [Alignment][NFC] Migrate the rest of backends · 1778564f
  Guillaume Chatelet authored Jun 05, 2020
  1778564f
Jun 07, 2020
- [RISCV] Fix a typo in RISCVISelLowering.cpp · 4b6f0ea6
  Ben Shi authored Jun 06, 2020
  4b6f0ea6
May 29, 2020
- Add NoMerge MIFlag to avoid MIR branch folding · 80e107cc
  Zequan Wu authored May 29, 2020
  80e107cc
May 23, 2020
- [MC] Change MCCFIInstruction::createDefCfaOffset to cfiDefCfaOffset which does not negate Offset · 0840d725
  Fangrui Song authored May 22, 2020
  0840d725
- [MC] Change MCCFIInstruction::createDefCfa to cfiDefCfa which does not negate Offset · 7e49dc61
  Fangrui Song authored May 22, 2020
  7e49dc61
May 22, 2020
- [RISCV] Register null target streamer for RISC-V · 22ed7249
  Pengxuan Zheng authored May 20, 2020
  22ed7249
- [Target] Use Align in TargetLoweringObjectFile::getSectionForConstant. · f96a7706
  Craig Topper authored May 21, 2020
  f96a7706
May 12, 2020
- Revert "[RISCV] Make CanLowerReturn protected for downstream maintenance" · 9d6064ec
  Jim Lin authored May 12, 2020
  9d6064ec
- [RISCV] Make CanLowerReturn protected for downstream maintenance · d775841d
  Jim Lin authored May 12, 2020
  d775841d
May 11, 2020
- [RISCV] Support Constant Pools in Load/Store Peephole · 969e7034
  Sam Elliott authored May 11, 2020
  969e7034
- Revert "[RISCV] Support Constant Pools in Load/Store Peephole" · 3242e565
  Sam Elliott authored May 11, 2020
  3242e565
- [RISCV] Support Constant Pools in Load/Store Peephole · fe69dfeb
  Sam Elliott authored May 11, 2020
  fe69dfeb
May 09, 2020
- [SelectionDAG] Use Align/MaybeAlign for ConstantPoolSDNode. · d1119980
  Craig Topper authored May 08, 2020
  d1119980
May 05, 2020
- [RISCV] Update debug scratch register names · 85aff8a4
  Pengxuan Zheng authored Apr 23, 2020
  85aff8a4
- [NFC][CostModel] Add TargetCostKind to relevant APIs · 40574fef
  Sam Parker authored Apr 28, 2020
  40574fef