Commits · e39b41931264d9f774dbe151bb64f4b579cf1ee0 · Roger Ferrer / llvm-epi · GitLab

Feb 10, 2022
- [Attributor][FIX] Honor alloca address space in AAPrivatizablePtr · e39b4193
  Johannes Doerfert authored Feb 07, 2022
  e39b4193
- [TTI][X86] Pull out repeated getSizeInBits() calls. NFC. · 8c82d42e
  Simon Pilgrim authored Feb 10, 2022
  
  8c82d42e
- Wild guess to fix LLDB bot · 695b629e
  Renato Golin authored Feb 10, 2022
  
  695b629e
- [gn build] Port bd3a1de6 · 8df4766e
  LLVM GN Syncbot authored Feb 10, 2022
  
  8df4766e
- [clang-cl] Support the /JMC flag · bd3a1de6
  Yuanfang Chen authored Feb 10, 2022
  bd3a1de6
- [AArch64][LoadStoreOptimizer] Ignore undef registers when checking rename... · 1d74b531
  Huihui Zhang authored Feb 10, 2022
  1d74b531
- [X86] Add smulo and umulo with add+load test coverage · 5565b38a
  Simon Pilgrim authored Feb 10, 2022
  
  5565b38a
- [RISCV] Lower the shufflevector equivalent of vector.splice · b0e77d5e
  Craig Topper authored Feb 10, 2022
  b0e77d5e
- [RISCV] Move the creation of VLMaxSentinel to isel. Use X0 during lowering. · b861ddf3
  Craig Topper authored Feb 10, 2022
  b861ddf3
- [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED. · 02e0d50e
  Paul Walker authored Feb 09, 2022
  02e0d50e
- [X86] Add tests showing failure to use LEA to avoid spoiling EFLAGS from smulo · 039a88be
  Simon Pilgrim authored Feb 10, 2022
  039a88be
- [X86] getFMA3OpcodeToCommuteOperands - use unreachable to detect fma3 format mismatch · e95fc20f
  Simon Pilgrim authored Feb 10, 2022
  e95fc20f
- [hwasan][test] Rework memaccess-clobber.ll · be2227b6
  Arthur Eubanks authored Feb 09, 2022
  be2227b6
- [RISCV] Remove stale comment. NFC · 727cd520
  Craig Topper authored Feb 10, 2022
  727cd520
- [DebugInfo][InstrRef] Avoid duplicate instruction numbers in x86-lea-fixup · 662799c8
  Jeremy Morse authored Feb 10, 2022
  662799c8
- [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection · d88a146f
  alex-t authored Feb 09, 2022
  d88a146f
- [AMDGPU] Pull out repeated getVecSize() calls. NFC. · 8de72973
  Simon Pilgrim authored Feb 10, 2022
  8de72973
- [AArch64] Improve codegen for get.active.lane.mask when SVE is available · 8b58494c
  David Sherwood authored Jan 05, 2022
  8b58494c
- [LV] Add tests with chained first-order recurrences. · f9779512
  Florian Hahn authored Feb 10, 2022
  
  f9779512
- [gn build] Port 9d905319 · 1e421108
  LLVM GN Syncbot authored Feb 10, 2022
  
  1e421108
- [InstSimplify] Remove zero-index opaque pointer GEP · 87a0b1bd
  Nikita Popov authored Feb 10, 2022
  87a0b1bd
- [AMDGPU] Rename DSAtomicCmpXChg to DSAtomicCmpXChgSwapped. NFC. · e34623b1
  Jay Foad authored Feb 10, 2022
  e34623b1
- [SVE] Remove redundant hasBF16 calls from lowering code. · 9cc7eb0e
  Paul Walker authored Feb 08, 2022
  9cc7eb0e
- [NFC][SCEV] `createNodeForSelectOrPHIViaUMinSeq()`: refactor `i1 cond ? i1 x : i1 y` handling · 580d3a14
  Roman Lebedev authored Feb 10, 2022
  580d3a14
- [NFC][SCEV] `createNodeForSelectOrPHIViaUMinSeq()`: refactor `i1 cond ? i1 C : i1 y` pattern · 9a322e43
  Roman Lebedev authored Feb 10, 2022
  9a322e43
- [NFC][SCEV] `createNodeForSelectOrPHIViaUMinSeq()`: refactor `i1 cond ? i1 x : i1 C` pattern · 576a45f2
  Roman Lebedev authored Feb 10, 2022
  576a45f2
- [SCEV] Recognize `cond ? i1 0 : i1 y` as `umin_seq ~cond, x` · 9766a0cc
  Roman Lebedev authored Feb 10, 2022
  9766a0cc
- [SCEV] Recognize `cond ? i1 x : i1 1` as `~umin_seq cond, ~x` · 418604fd
  Roman Lebedev authored Feb 10, 2022
  418604fd
- [SCEV] Recognize logical `or` as `not umin_seq (not, not)` · 49d9acc2
  Roman Lebedev authored Feb 10, 2022
  49d9acc2
- [SCEV] Recognize logical `and` as `umin_seq` · 16bc24e7
  Roman Lebedev authored Feb 10, 2022
  16bc24e7
- [SCEV] `createNodeForSelectOrPHI()`: try constant-folding even if not an Instruction · 1c694448
  Roman Lebedev authored Feb 10, 2022
  1c694448
- [NFC][SCEV] Prepare `createNodeForSelectOrPHI()` for gaining additional strategy · 97930f85
  Roman Lebedev authored Feb 10, 2022
  97930f85
- [SCEV] Recognize binary `xor` as bit-wise `add` · 73990ff8
  Roman Lebedev authored Feb 10, 2022
  73990ff8
- [SCEV] Recognize binary `and` as bit-wise `umin` · 503541fa
  Roman Lebedev authored Feb 10, 2022
  503541fa
- [SCEV] Recognize binary `or` as bit-wise `umax` · e7e0834f
  Roman Lebedev authored Feb 10, 2022
  e7e0834f
- [NFC][SCEV] Add some tests with logical operations and whatnot · 0e6e559b
  Roman Lebedev authored Feb 10, 2022
  
  0e6e559b
- [SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD. · c58be857
  Paul Walker authored Feb 08, 2022
  c58be857
- [SVE][CodeGen] Bail out for scalable vectors in AArch64TargetLowering::ReconstructShuffle · a57a7f3d
  David Sherwood authored Jan 04, 2022
  a57a7f3d
- [InstCombine] Extend fold (icmp sgt smin(PosA, B) 0) -> (icmp sgt B 0) to support smin intrinsic · aca355a3
  Simon Pilgrim authored Feb 10, 2022
  aca355a3
- [InstCombine] Add test showing failure to fold (icmp sgt smin(PosA, B) 0) ->... · 4b1525b9
  Simon Pilgrim authored Feb 10, 2022
  4b1525b9