Commits · e3bb0a72b6ad2264f552d6e2769a4ce63bb46ed9 · Roger Ferrer / llvm-epi · GitLab

Jul 11, 2019
- [MIPS GlobalISel] RegBankSelect for chains of ambiguous instructions · e3bb0a72
  Petar Avramovic authored Jul 11, 2019
  e3bb0a72
- [ARM][ParallelDSP] Change the search for smlads · 85ad78b1
  Sam Parker authored Jul 11, 2019
  85ad78b1
- [WebAssembly] Print error message for llvm.clear_cache intrinsic · 54c136bb
  Heejin Ahn authored Jul 11, 2019
  54c136bb
- [X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass. · 88729e3d
  Craig Topper authored Jul 11, 2019
  88729e3d
- [AMDGPU] gfx908 atomic fadd and atomic pk_fadd · e93279fd
  Stanislav Mekhanoshin authored Jul 11, 2019
  e93279fd
- [AMDGPU] gfx908 dot instruction support · c0ae1be0
  Stanislav Mekhanoshin authored Jul 11, 2019
  c0ae1be0
- [SDAG] commute setcc operands to match a subtract · 138328e4
  Sanjay Patel authored Jul 10, 2019
  138328e4
- [X86] Add patterns with and_flag_nocf for BLSI and TBM instructions. · 1c327c7e
  Craig Topper authored Jul 10, 2019
  1c327c7e
- [X86] Add a few more TBM and BLSI test cases that show the same issue that r352306 fixed for BLSR. · 472ad62b
  Craig Topper authored Jul 10, 2019
  472ad62b
Jul 10, 2019
- [AArch64][GlobalISel] Optimize compare and branch cases with G_INTTOPTR and unknown values. · 7a4d2df0
  Amara Emerson authored Jul 10, 2019
  7a4d2df0
- [GlobalISel][AArch64] Use getOpcodeDef instead of findMIFromReg · 7c95925b
  Jessica Paquette authored Jul 10, 2019
  7c95925b
- [GlobalISel][AArch64][NFC] Use getDefIgnoringCopies from Utils where we can · 3132968a
  Jessica Paquette authored Jul 10, 2019
  3132968a
- Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe... · f4572249
  Michael Berg authored Jul 10, 2019
  f4572249
- [X86] Regenerate tests. NFCI. · 5a6d40be
  Simon Pilgrim authored Jul 10, 2019
  5a6d40be
- [X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsics. NFC · ab5a30ac
  Craig Topper authored Jul 10, 2019
  ab5a30ac
- [TargetLowering] support BlockAddress as "i" inline asm constraint · 8728e457
  Nick Desaulniers authored Jul 10, 2019
  8728e457
- GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM · 6ce1b4fe
  Matt Arsenault authored Jul 10, 2019
  6ce1b4fe
- GlobalISel: Define the full family of FP min/max instructions · e595a2c9
  Matt Arsenault authored Jul 10, 2019
  e595a2c9
- AMDGPU: Serialize mode from MachineFunctionInfo · 58426a37
  Matt Arsenault authored Jul 10, 2019
  58426a37
- [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32 · bba37e89
  Jay Foad authored Jul 10, 2019
  bba37e89
- [MIPS GlobalISel] Select float and double phi · 7d0778ea
  Petar Avramovic authored Jul 10, 2019
  7d0778ea
- [MIPS GlobalISel] Select float and double load and store · 7b31491a
  Petar Avramovic authored Jul 10, 2019
  7b31491a
- [X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support · 6a585839
  Simon Pilgrim authored Jul 10, 2019
  6a585839
- AMDGPU/GlobalISel: Add support for wide loads >= 256-bits · d0ba79fe
  Tom Stellard authored Jul 10, 2019
  d0ba79fe
- GlobalISel: Implement lower for G_FCOPYSIGN · b1843e13
  Matt Arsenault authored Jul 09, 2019
  b1843e13
- AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR · 3f1a3454
  Matt Arsenault authored Jul 09, 2019
  3f1a3454
- GlobalISel: Combine unmerge of merge with intermediate cast · 14a44951
  Matt Arsenault authored Jul 09, 2019
  14a44951
Jul 09, 2019
- hwasan: Improve precision of checks using short granule tags. · 1366262b
  Peter Collingbourne authored Jul 09, 2019
  1366262b
- [X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into... · 84a1f073
  Craig Topper authored Jul 09, 2019
  84a1f073
- [AMDGPU] gfx908 register file changes · 9e77d0c6
  Stanislav Mekhanoshin authored Jul 09, 2019
  9e77d0c6
- Boilerplate for producing XCOFF object files from the PowerPC backend. · f09d54ed
  Sean Fertile authored Jul 09, 2019
  f09d54ed
- [AMDGPU] gfx908 target · 22b2c3d6
  Stanislav Mekhanoshin authored Jul 09, 2019
  22b2c3d6
- AMDGPU: Fix test failing since r365512 · 077df019
  Matt Arsenault authored Jul 09, 2019
  077df019
- [AMDGPU] Created a sub-register class for the return address operand in the return instruction. · b2d24bd5
  Christudasan Devadasan authored Jul 09, 2019
  b2d24bd5
- [RISCV] Fix ICE in isDesirableToCommuteWithShift · 114d2db4
  Sam Elliott authored Jul 09, 2019
  114d2db4
- [AArch64][GlobalISel] Optimize conditional branches followed by unconditional branches · 6616e269
  Amara Emerson authored Jul 09, 2019
  6616e269
- [mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU · e3892d84
  Simon Atanasyan authored Jul 09, 2019
  e3892d84
- [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC · 623282f0
  Simon Atanasyan authored Jul 09, 2019
  623282f0
- [BPF] Support for compile once and run everywhere · d3d88d08
  Yonghong Song authored Jul 09, 2019
  d3d88d08
- [ARM] Add test for MVE and no floats. NFC · 781e3aff
  David Green authored Jul 09, 2019
  781e3aff