Commits · e4a9190ad7b20a12476e3cccc30e842c0a93f1bb · Roger Ferrer / llvm-epi · GitLab

Apr 25, 2020
- [X86][ArgumentPromotion] Allow Argument Promotion if caller and callee... · e4a9190a
  Craig Topper authored Apr 24, 2020
  e4a9190a
- Use .text.unlikely and .text.eh prefixes for MachineBasicBlock sections. · 0cc063a8
  Snehasish Kumar authored Apr 24, 2020
  0cc063a8
Apr 24, 2020
- [XRay] Change Sled.Function to PC-relative for sled version 2 and make... · 10bc1258
  Fangrui Song authored Apr 24, 2020
  10bc1258
- [AArch64][GlobalISel] Fix sub-64b stack parameter passing on Darwin. · dbb03567
  Amara Emerson authored Apr 24, 2020
  dbb03567
- [CostModel][X86][ARM] Teach getCastInstrCost to include the splitting factor... · 03aa967c
  Craig Topper authored Apr 24, 2020
  03aa967c
- [RISCV] Add instruction definition for dret · 79702dd3
  Pengxuan Zheng authored Apr 24, 2020
  79702dd3
- AMDGPU: Break read2/write2 search range on a memory fence · 35e6a9c8
  Matt Arsenault authored Apr 24, 2020
  35e6a9c8
- [AssumeBundles] Use assume bundles in isKnownNonZero · 42431da8
  Tyker authored Apr 24, 2020
  42431da8
- AArch64: Remove reversedInstructionsWithoutDebug helper · c0fa447e
  Vedant Kumar authored Apr 24, 2020
  c0fa447e
- [InstCombine] regenerate test checks; NFC · 238f00f6
  Sanjay Patel authored Apr 24, 2020
  238f00f6
- [CostModel][X86] Account for splitting cost when vector zext/sext type... · 4cf73a3f
  Craig Topper authored Apr 23, 2020
  4cf73a3f
- [llvm][NFC] Factor out inlining pipeline as a module pipeline. · c3770c5d
  Mircea Trofin authored Apr 20, 2020
  c3770c5d
- [InstCombine] intersect FMF when reassociating FP min/max intrinsics · e4175ff5
  Sanjay Patel authored Apr 24, 2020
  e4175ff5
- [AArch64] Allow PAC mnemonics in the HINT space with PAC disabled · d4e7b000
  Pablo Barrio authored Mar 10, 2020
  d4e7b000
- [XRay] Change ARM/AArch64/powerpc64le to use version 2 sled (PC-relative address) · 25e22613
  Fangrui Song authored Apr 21, 2020
  25e22613
- [AArch32] Armv8.6a Matrix Mul Assembly Parsing Support · 659ca502
  Luke Geeson authored Apr 09, 2020
  659ca502
- [AArch64] Armv8.6-A Mat Mul SVE Assembly · e7146838
  Luke Geeson authored Apr 09, 2020
  e7146838
- [AArch32] Armv8.6-a Matrix Mult Assembly + Intrinsics · 7da19051
  Luke Geeson authored Apr 09, 2020
  7da19051
- [AArch64] Armv8.6-a Matrix Mult Assembly + Intrinsics · 832cd749
  Luke Geeson authored Apr 09, 2020
  832cd749
- [obj2yaml] - Program headers: simplify the computation of p_filesz. · 9f9a08e1
  Georgii Rymar authored Apr 22, 2020
  9f9a08e1
- [AMDGPU] Skip generating cache invalidating instructions on AMDPAL · 7631af3a
  Piotr Sobczak authored Apr 24, 2020
  7631af3a
- [ARM] Various tests for MVE and FP16 codegen. NFC · a947be51
  David Green authored Apr 23, 2020
  
  a947be51
- [SVE][CodeGen] Lower SDIV & UDIV to SVE intrinsics · 53dd72a8
  Kerry McLaughlin authored Apr 24, 2020
  53dd72a8
- [LoopVectorize] Preserve CFG analyses if CFG wasn't modified · 9cd4debd
  Max Kazantsev authored Apr 24, 2020
  9cd4debd
- [NFC][PowerPC] Fix the liveins for 3 mir test cases · 302e11cd
  Kang Zhang authored Apr 24, 2020
  
  302e11cd
- [AMDGPU] Add the SGPR used for FP copy to block livein lists. · 207cd5f6
  Christudasan Devadasan authored Apr 23, 2020
  207cd5f6
- [Attributor][NFC] Remove and update old check lines · 10ff24d8
  Johannes Doerfert authored Apr 22, 2020
  
  10ff24d8
- [Attributor][NFC] Strip check lines not used while 3 tests are partially disable · a6b14bae
  Johannes Doerfert authored Apr 22, 2020
  a6b14bae
- [ValueTracking] Handle shufflevector constants in ComputeNumSignBits · 3291efc2
  Eli Friedman authored Apr 22, 2020
  3291efc2
- [Hexagon] Fix result word order when bitcasting vector pred to int64/128 · 5c7a2cfa
  Krzysztof Parzyszek authored Apr 23, 2020
  
  5c7a2cfa
- Change callbr to only define its output SSA variable on the normal · 248a5db3
  James Y Knight authored Apr 16, 2020
  248a5db3
- [llvm] [CodeGen] Fixed vector halving bug for masked load · 907871d9
  aartbik authored Apr 23, 2020
  907871d9
- [llvm] [X86] Processed test with update_llc_test_checks · e4e187d2
  aartbik authored Apr 23, 2020
  e4e187d2
Apr 23, 2020
- [x86] add tests for FP->int->FP with different FP types; NFC · b53fd70b
  Sanjay Patel authored Apr 23, 2020
  
  b53fd70b
- [InstCombine] Negator: don't negate multi-use `sub` · 5a159ed2
  Roman Lebedev authored Apr 23, 2020
  5a159ed2
- [AMDGPU] Avoid hard-coded line numbers in error message checks · 479145a5
  Jay Foad authored Apr 23, 2020
  479145a5
- AMDGPU: Fix inlining logic for denormals · 156afb22
  Matt Arsenault authored Apr 22, 2020
  156afb22
- AMDGPU: Change pre-gfx9 implementation of fcanonicalize to mul · 89c8c80b
  Matt Arsenault authored Apr 22, 2020
  89c8c80b
- [llvm-objcopy][MachO] Copy LC_LOAD_WEAK_DYLIB load commands · d987eed9
  Alexander Shaposhnikov authored Apr 23, 2020
  d987eed9
- AMDGPU/GlobalISel: Add new baseline checks for canonicalize · 5fe3f065
  Matt Arsenault authored Apr 23, 2020
  
  5fe3f065