Commits · e4c1dfed38370b4933f05c8e24b1d77df56b526c · Roger Ferrer / llvm-epi · GitLab

Mar 21, 2023
- [X86] Create extra prolog/epilog for stack realignment · e4c1dfed
  Luo, Yuanke authored Mar 09, 2023
  e4c1dfed
Mar 20, 2023
- [PowerPC][NFC] Test needs to include constant pool values · 6ee4ea8e
  Nemanja Ivanovic authored Mar 20, 2023
  
  6ee4ea8e
- [PowerPC][NFC] Pre-commit a test case for upcoming patch · da40f7e8
  Nemanja Ivanovic authored Mar 20, 2023
  
  da40f7e8
- [AArch64] Regenerate neon-vcmla.ll tests and add tests for combining fadd with vcmla. NFC · cd22e7c3
  David Green authored Mar 20, 2023
  cd22e7c3
- Revert "Revert "[SVE] Add patterns for shift intrinsics with FalseLanesZero mode"" · 8d6ab7d5
  Muhammad Omair Javaid authored Mar 20, 2023
  8d6ab7d5
- Revert "[SVE] Add patterns for shift intrinsics with FalseLanesZero mode" · 32bd1f56
  Muhammad Omair Javaid authored Mar 20, 2023
  32bd1f56
Mar 19, 2023
- [SVE] Add patterns for shift intrinsics with FalseLanesZero mode · 22c3ba4b
  lizhijin authored Mar 19, 2023
  22c3ba4b
Mar 18, 2023
- [AMDGPU] Reserve extra SGPR blocks wth XNACK "any" TID Setting · 864a2b25
  Austin Kerbow authored Mar 06, 2023
  864a2b25
- [WebAssembly] Replace Bugzilla links with Github issues · 4e844a14
  Heejin Ahn authored Mar 13, 2023
  4e844a14
- [NVPTX] Report fatal error on empty argument type. · 7adacaa0
  Pavel Kopyl authored Mar 16, 2023
  7adacaa0
Mar 17, 2023
- [RISCV] Add isReMaterializable to FLI instructions. · 101cf0b8
  Craig Topper authored Mar 17, 2023
  101cf0b8
- [RISCV] Add isAsCheapAsAMove to FLI instructions. · 0a895c39
  Craig Topper authored Mar 17, 2023
  0a895c39
- [RISCV] Add test case showing fli being hoisted out of a loop and creating extra copies/spills. · f36ec414
  Craig Topper authored Mar 17, 2023
  f36ec414
- CodeGen: Reorder case handling for is.fpclass legalization · 9356ec15
  Matt Arsenault authored Feb 02, 2023
  9356ec15
- [Hexagon] Ensure proper ordering of instructions in HVC::AlignVectors · 0eac3c50
  Krzysztof Parzyszek authored Mar 17, 2023
  0eac3c50
- [SCEVExpander] Always use scevgep as name · 687b5b9a
  Nikita Popov authored Mar 17, 2023
  687b5b9a
- [RISCV] Add MULW to RISCVStripWSuffix. · 4063369f
  Craig Topper authored Mar 16, 2023
  4063369f
- Revert "[AMDGPUUnifyDivergentExitNodes] Add NewPM support" · aa15fe98
  Vitaly Buka authored Mar 16, 2023
  aa15fe98
Mar 16, 2023
- [AIX] unset bit "IsBackChainStored" of traceback table for leaf functions with no stack frame · 49bc3077
  zhijian authored Mar 16, 2023
  49bc3077
- [AMDGPU] Select flat atomic fmin/fmax · d5c0c1b6
  Mirko Brkusanin authored Mar 16, 2023
  d5c0c1b6
- [RISCV] Fix missing addi in test to validate lower inline asm m with offset · 185ea867
  Mikhail R. Gadelha authored Mar 16, 2023
  
  185ea867
- [AMDGPUUnifyDivergentExitNodes] Add NewPM support · a5455e32
  Anshil Gandhi authored Mar 16, 2023
  a5455e32
- [RISCV] Added tests to validate lower inline asm m and A with offsets · 4bbee03d
  Mikhail R. Gadelha authored Mar 16, 2023
  
  4bbee03d
- Recommit DwarfEHPrepare: insert extra unwind paths for stack protector to instrument · 2d690684
  Tim Northover authored Feb 07, 2023
  2d690684
- Revert "DwarfEHPrepare: insert extra unwind paths for stack protector to instrument" · e4b352a0
  Tim Northover authored Mar 16, 2023
  e4b352a0
- DwarfEHPrepare: insert extra unwind paths for stack protector to instrument · 203b6f31
  Tim Northover authored Feb 07, 2023
  203b6f31
- [ConstExpr] Remove select constant expression · bbfb13a5
  Nikita Popov authored Mar 06, 2023
  bbfb13a5
- [LoongArch] Emit bytepick for picking from concatenation of two values · 19e2ebbf
  WANG Xuerui authored Mar 16, 2023
  19e2ebbf
- [LoongArch] Add baseline tests for `bytepick` codegen. NFC · ff475a0d
  WANG Xuerui authored Mar 16, 2023
  ff475a0d
- [RISCV]Optimize (riscvisd::select_cc x, 0, ne, x, 1) · fc973037
  LiaoChunyu authored Mar 16, 2023
  fc973037
- [Clang][LoongArch] Implement patchable function entry · db5dfec9
  WANG Xuerui authored Mar 15, 2023
  db5dfec9
Mar 15, 2023
- [AArch64] Add hex comments to mov-imm spellings in the InstPrinter · aba4e4d6
  Jon Roelofs authored Mar 14, 2023
  aba4e4d6
- Revert "[AArch64] Add hex comments to mov-imm spellings in the InstPrinter" · cdee83b0
  Jon Roelofs authored Mar 15, 2023
  cdee83b0
- [AArch64] Add hex comments to mov-imm spellings in the InstPrinter · 1def3141
  Jon Roelofs authored Mar 14, 2023
  1def3141
- [AArch64] Change GeneratePerfectShuffle to return one destination operand for... · 4b09d7a8
  Zain Jaffal authored Mar 15, 2023
  4b09d7a8
- [X86] lzcnt-cmp.ll - enable CMOV on 32-bit LZCNT tests · 5be55100
  Simon Pilgrim authored Mar 15, 2023
  5be55100
- [DAG] Don't fold zext(logicalshift(zext(x),c)) -> logicalshift(zext(x),c) if the outer zext is free · 28a0d0e8
  Simon Pilgrim authored Mar 15, 2023
  28a0d0e8
- [X86] Add more thorough testing of the zext(logicalshift(zext(x),c)) ->... · 2281286e
  Simon Pilgrim authored Mar 15, 2023
  2281286e
- [codegen][riscv] Emit CFI directives when using shadow call stack · ade336d6
  Paul Kirth authored Mar 02, 2023
  ade336d6
- [AMDGPU] Update mul.ll with auto-generated checks · 6bc5aa59
  Konstantina Mitropoulou authored Mar 13, 2023
  6bc5aa59