Commits · e4d22d59d1db39262790b6afd3521a65be2d7288 · Roger Ferrer / llvm-epi · GitLab

Jul 21, 2015
- Targets: commonize some stack realignment code · e4d22d59
  JF Bastien authored Jul 20, 2015
  e4d22d59
- AArch64: Add aditional Cyclone macroop fusion opportunities · e536f4f6
  Matthias Braun authored Jul 20, 2015
  e536f4f6
- Fix comment typo (test commit). NFC · e41c2df0
  Geoff Berry authored Jul 20, 2015
  e41c2df0
Jul 20, 2015
- [ARM] Refactor the prologue/epilogue emission to be more robust. · 71a71485
  Quentin Colombet authored Jul 20, 2015
  71a71485
- [NVPTX] make load on global readonly memory to use ldg · 48a9bdc6
  Jingyue Wu authored Jul 20, 2015
  48a9bdc6
- [Hexagon] Generate MUX from conditional transfers when dot-new not possible · 92172204
  Krzysztof Parzyszek authored Jul 20, 2015
  92172204
- [ImplicitNullChecks] Work with implicit defs. · 93d608c3
  Sanjoy Das authored Jul 20, 2015
  93d608c3
- [AArch64] Change EON pattern to match more often. · 3da0ea7f
  Chad Rosier authored Jul 20, 2015
  3da0ea7f
- AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops · 70580f83
  Tom Stellard authored Jul 20, 2015
  70580f83
- [mips] Added support for the ERETNC instruction. · 974d4092
  Vasileios Kalintiris authored Jul 20, 2015
  974d4092
Jul 19, 2015
- [X86][SSE] Reordered cast vectorization costs. NFCI. · e2c244f3
  Simon Pilgrim authored Jul 19, 2015
  e2c244f3
- [X86] Add support for tbyte memory operand size for Intel-syntax x86 assembly · 69e40a4c
  Michael Kuperstein authored Jul 19, 2015
  69e40a4c
- Remove TargetInstrInfo::canFoldMemoryOperand · ba51d116
  Simon Pilgrim authored Jul 19, 2015
  ba51d116
- AVX-512: Floating point conversions for SKX - DAG Lowering. · 17b90605
  Elena Demikhovsky authored Jul 19, 2015
  17b90605
Jul 18, 2015
- [X86][SSE] Updated SHL/LSHR i64 vectorization costs. · 59764dcc
  Simon Pilgrim authored Jul 18, 2015
  59764dcc
- [Hexagon] Use composition instead of inheritance from STL types · 9a5d7889
  Benjamin Kramer authored Jul 18, 2015
  9a5d7889
- ARM: Enable MachineScheduler and disable PostRAScheduler for swift. · 9e859806
  Matthias Braun authored Jul 17, 2015
  9e859806
- ARM: Add scheduling information for LDRLIT instructions to swift scheduling model · 141d1c9d
  Matthias Braun authored Jul 17, 2015
  141d1c9d
Jul 17, 2015
- Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift." · 5a6d5bc1
  Adam Nemet authored Jul 17, 2015
  5a6d5bc1
- [ARM] Use [SU]ABSDIFF nodes instead of intrinsics for VABD/VABA · a6702e2f
  James Molloy authored Jul 17, 2015
  a6702e2f
- [AArch64] Use [SU]ABSDIFF nodes instead of intrinsics for ABD/ABA · faf4e3c3
  James Molloy authored Jul 17, 2015
  faf4e3c3
- Use inbounds GEPs for memcpy and memset lowering · b09cfb51
  Eli Bendersky authored Jul 17, 2015
  b09cfb51
- AArch64: add comment missed out from earlier patch. · a5740e08
  Tim Northover authored Jul 17, 2015
  a5740e08
- ARM: Enable MachineScheduler and disable PostRAScheduler for swift. · 2d8315f8
  Matthias Braun authored Jul 17, 2015
  2d8315f8
- Use small encodings for constants when possible. · 494a381e
  Rafael Espindola authored Jul 17, 2015
  494a381e
- Arm: Don't define a label twice with two setjmps in a function. · da3d0d73
  Matthias Braun authored Jul 16, 2015
  da3d0d73
- Fix __builtin_setjmp in combination with sjlj exception handling. · 3cd00c17
  Matthias Braun authored Jul 16, 2015
  3cd00c17
Jul 16, 2015
- Fix spelling. NFCI. · 91525289
  Simon Pilgrim authored Jul 16, 2015
  91525289
- AArch64: make inexact signalling on round Darwin-specific · ca0ffc35
  Tim Northover authored Jul 16, 2015
  ca0ffc35
- [PowerPC] v4i32 is a VSRCRegClass · 54cced54
  Bill Schmidt authored Jul 16, 2015
  54cced54
- Streamline the coding style in NVPTXLowerAggrCopies · f871e09d
  Eli Bendersky authored Jul 16, 2015
  f871e09d
- [NVPTX] enable SpeculativeExecution in NVPTX · e7981cee
  Jingyue Wu authored Jul 16, 2015
  e7981cee
- AArch64: Implement conditional compare sequence matching. · af7d7709
  Matthias Braun authored Jul 16, 2015
  af7d7709
- AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand · 78655fcf
  Tom Stellard authored Jul 16, 2015
  78655fcf
- AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets · c98ee203
  Tom Stellard authored Jul 16, 2015
  c98ee203
- Revert "Add missing load/store flags to thumb2 instructions." · f4ce569d
  Pete Cooper authored Jul 16, 2015
  f4ce569d
- [NVPTX] Don't leak dead instructions after unlinking them from the BasicBlock · 5dfd8b6d
  Benjamin Kramer authored Jul 16, 2015
  5dfd8b6d
- Correct lowering of memmove in NVPTX · f14af162
  Eli Bendersky authored Jul 16, 2015
  f14af162
- AMDGPU/R600: Remove unused variable · ff5efb8c
  Tom Stellard authored Jul 16, 2015
  ff5efb8c
- AMDPGU/R600: Replace llvm_unreachable() call with LLVMContext::emitError() · 1d46fb2d
  Tom Stellard authored Jul 16, 2015
  1d46fb2d