Commits · e4ecd83fe969c77c23f7a5bd4d5ed521550b5737 · Roger Ferrer / llvm-epi · GitLab

Jun 16, 2021
- [llvm][AArch64] Handle arrays of struct properly (from IR) · e4ecd83f
  David Spickett authored Jun 09, 2021
  e4ecd83f
- [X86][AVX] Regenerate pr15296.ll tests · 39efbf91
  Simon Pilgrim authored Jun 16, 2021
  39efbf91
- [SVE] Fix PromoteIntRes_TRUNCATE not to call getVectorNumElements · dab05335
  Dylan Fleming authored Jun 16, 2021
  dab05335
- [ARM] Correct type of setcc results for FP vectors · 0a714eaa
  David Green authored Jun 16, 2021
  0a714eaa
- [ARM] Extra tests for sign extended floating point compares. NFC · 3f18fc5e
  David Green authored Jun 16, 2021
  
  3f18fc5e
- Revert "[SampleFDO] Using common linkage for the discriminator flag variable" · 95f9026c
  Rong Xu authored Jun 15, 2021
  95f9026c
- X86: balance the frame prologue and epilogue on Win64 · 17bdc0ff
  Saleem Abdulrasool authored Jun 13, 2021
  17bdc0ff
Jun 15, 2021
- [SampleFDO] Using common linkage for the discriminator flag variable · 434fed5a
  Rong Xu authored Jun 15, 2021
  434fed5a
- [PowerPC] Fix spilling of paired VSX registers · 821a8f68
  Nemanja Ivanovic authored Jun 15, 2021
  821a8f68
- [X86] avoid assert with varargs, soft float, and no-implicit-float · 3bc899b4
  Bob Haarman authored Jun 09, 2021
  3bc899b4
- [AMDGPU] Fix lds superalign test. NFC. · a1188046
  Stanislav Mekhanoshin authored Jun 15, 2021
  
  a1188046
- Revert "[ARM] Extend narrow values to allow using truncating scatters" · 93aa445e
  David Green authored Jun 15, 2021
  93aa445e
- [ARM] Extend narrow values to allow using truncating scatters · b9bd2936
  David Green authored Jun 15, 2021
  b9bd2936
- [ARM] Use rq gather/scatters for smaller v4 vectors · 680d3f8f
  David Green authored Jun 15, 2021
  680d3f8f
- [ARM] Rejig some of the MVE gather/scatter lowering pass. NFC · 09924cba
  David Green authored Jun 15, 2021
  09924cba
- [X86] Use EVT::getVectorVT instead of changeVectorElementType in reduceVMULWidth. · 4017d033
  Craig Topper authored Jun 14, 2021
  4017d033
- [PowerPC] Export 16 byte load-store instructions · 1c450c3d
  Kai Luo authored Jun 15, 2021
  1c450c3d
- [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE. · 1c096bf0
  Huihui Zhang authored Jun 14, 2021
  1c096bf0
Jun 14, 2021
- [TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0)) · 585e65d3
  Roman Lebedev authored Jun 14, 2021
  585e65d3
- X86: pass swift_async context in R14 on Win64 · 8c8dbc10
  Saleem Abdulrasool authored Jun 13, 2021
  8c8dbc10
- [RISCV] Transform unaligned RVV vector loads/stores to aligned ones · c75e454c
  Fraser Cormack authored Jun 09, 2021
  c75e454c
- [AIX][XCOFF] emit vector info of traceback table. · 7ed515d1
  zhijian authored Jun 14, 2021
  7ed515d1
- [AArch64] Improve SAD pattern · 08ce52ef
  Jingu Kang authored Jun 10, 2021
  08ce52ef
- [DAGCombine] reduceBuildVecToShuffle(): sort input vectors by decreasing size · 6e562835
  Roman Lebedev authored Jun 14, 2021
  6e562835
- Implement DW_CFA_LLVM_* for Heterogeneous Debugging · 167e7afc
  RamNalamothu authored Jun 14, 2021
  167e7afc
Jun 13, 2021
- [SPARC] Legalize truncation and extension between fp128 and half · 5be3a1a0
  LemonBoy authored Jun 13, 2021
  5be3a1a0
- [ARM] Introduce t2WhileLoopStartTP · bee2f618
  David Green authored Jun 13, 2021
  bee2f618
- [ARM][NEON] Combine base address updates for vld1Ndup intrinsics · f6b9836b
  Kristina Bessonova authored Jun 02, 2021
  f6b9836b
- [X86] Check immediate before get it. · 5be314f7
  Luo, Yuanke authored Jun 10, 2021
  5be314f7
- Revert "[X86] Check immediate before get it." · 1e72b9d5
  Luo, Yuanke authored Jun 13, 2021
  1e72b9d5
- [X86] Check immediate before get it. · 9eb2f723
  Luo, Yuanke authored Jun 10, 2021
  9eb2f723
Jun 12, 2021
- [NFC][X86][Codegen] Add shuffle test that would benefit from sorting in reduceBuildVecToShuffle() · 2db64e19
  Roman Lebedev authored Jun 13, 2021
  
  2db64e19
- [X86] Add ISD::FREEZE and ISD::AssertAlign to the list of opcodes that don't... · c997867d
  Craig Topper authored Jun 12, 2021
  c997867d
- Revert "[X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB" · 5cd66420
  Florian Hahn authored Jun 12, 2021
  5cd66420
- Revert "[X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization" · e087b4f1
  Florian Hahn authored Jun 12, 2021
  e087b4f1
- [AMDGPU][IndirectCalls] Fix register usage propagation for indirect/external calls · c27e8141
  madhur13490 authored Jun 03, 2021
  c27e8141
Jun 11, 2021
- [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated · 0aef747b
  Roman Lebedev authored Jun 11, 2021
  0aef747b
- [X86FixupLEAs] Sub register usage of LEA dest should block LEA/SUB optimization · f35bcea1
  Guozhi Wei authored Jun 11, 2021
  f35bcea1
- [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned · 773771ba
  Tomas Matheson authored Apr 20, 2021
  773771ba
- precommit tests for D104042 · 9eedde70
  Jingu Kang authored Jun 11, 2021
  
  9eedde70