Commits · e5972f2a04ee48a9190cd25f0d5b24cbca4d47f2 · Roger Ferrer / llvm-epi · GitLab

Oct 30, 2019
- [AMDGPU] Simplify VCCZ bug handling · e5972f2a
  Jay Foad authored Oct 30, 2019
  e5972f2a
- Fix pattern error for S2_tstbit_i instruction · 14e289eb
  Ikhlas Ajbar authored Oct 07, 2019
  14e289eb
- [AIX] Lowering CPI/JTI/BA to MIR · 5c9bdc79
  Xiangling Liao authored Oct 30, 2019
  5c9bdc79
- [AArch64][MachineOutliner] Return address signing for outlined functions · 70caa1fc
  David Tellenbach authored Oct 30, 2019
  70caa1fc
- [SelectionDAG] Add support for FP_ROUND in WidenVectorOperand. · 86549c75
  Jay Foad authored Oct 23, 2019
  86549c75
- [AArch64][SVE] Implement masked store intrinsics · 5c2c9464
  Kerry McLaughlin authored Oct 30, 2019
  5c2c9464
- [AArch64][SVE] Implement additional integer arithmetic intrinsics · e128c208
  Kerry McLaughlin authored Oct 30, 2019
  e128c208
- [PowerPC] Clear the sideeffect bit for those instructions that didn't have the match pattern · f15cf938
  QingShan Zhang authored Oct 30, 2019
  f15cf938
- [X86] Add test case for PR43758. NFC · bbe2fcbd
  Craig Topper authored Oct 29, 2019
  
  bbe2fcbd
- [X86] Make memcmp vector lowering handle arbitrary expansions · f68925d4
  David Zarzycki authored Oct 28, 2019
  f68925d4
- AMDGPU/GlobalISel: Legalize FDIV32 · 2b88b344
  Austin Kerbow authored Oct 29, 2019
  2b88b344
Oct 29, 2019
- [SelectionDAG] Enable lowering unordered atomics loads w/LoadSDNode (and... · 2460989e
  Philip Reames authored Oct 29, 2019
  2460989e
- [X86] Narrow i64 compares with constant to i32 when the upper 32-bits are known zero. · 772533d9
  Craig Topper authored Oct 29, 2019
  772533d9
- [X86][VBMI2] Add vector funnel shift tests · 55cfaec9
  Simon Pilgrim authored Oct 29, 2019
  55cfaec9
- [SVE][AArch64] Adding pattern matching for some SVE instructions. · 1e9de021
  Ehsan Amiri authored Oct 29, 2019
  1e9de021
- Reland [AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2) · d6a7da80
  Sander de Smalen authored Oct 29, 2019
  d6a7da80
- [Hexagon] Handle remaining registers in getRegisterByName() · 99f51960
  Krzysztof Parzyszek authored Oct 28, 2019
  99f51960
- Revert rG70f5aecedef9a6e347e425eb5b843bf797b95319 - "Reland... · 2c496bb5
  Simon Pilgrim authored Oct 29, 2019
  2c496bb5
- [BranchFolding] skip debug instr to avoid code change · ec32dff0
  Jeremy Morse authored Oct 29, 2019
  ec32dff0
- AMDGPU: Make VReg_1 only include 1 artificial register · 21bc8e5a
  Matt Arsenault authored Oct 28, 2019
  21bc8e5a
- [RISCV] Remove RA from reserved register to use as callee saved register · c1498e37
  Shiva Chen authored Oct 15, 2019
  c1498e37
- [PowerPC] Emit scalar fp min/max instructions · 25a41ad2
  Nemanja Ivanovic authored Oct 28, 2019
  25a41ad2
- Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs" · 74204304
  Amy Huang authored Oct 28, 2019
  74204304
Oct 28, 2019
- [AArch64][GlobalISel] Fix assertion fail in C++ selection for vector zext of <4 x s8> · 0f6ed432
  Amara Emerson authored Oct 27, 2019
  0f6ed432
- [PowerPC] Do not emit HW loop if the body contains calls to lrint/lround · 97e36260
  Nemanja Ivanovic authored Oct 28, 2019
  97e36260
- [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics · d9972f84
  Artem Belevich authored Oct 22, 2019
  d9972f84
- [Remarks] Remove references to ELF support · c7557dd6
  Francis Visoiu Mistrih authored Oct 28, 2019
  c7557dd6
- [Remarks] Emit the remarks section by default for certain formats · 209d5a12
  Francis Visoiu Mistrih authored Oct 28, 2019
  209d5a12
- Convert files added in d157a9bc to unix line endings. · e59f7488
  Nico Weber authored Oct 28, 2019
  e59f7488
- [X86] Add a DAG combine to turn (and (bitcast (vXi1 (concat_vectors (vYi1... · 3da269a2
  Craig Topper authored Oct 28, 2019
  3da269a2
- Reland [AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2) · 70f5aece
  Sander de Smalen authored Oct 28, 2019
  70f5aece
- AMDGPU: Avoid overwriting saved PC · d11b93ec
  Austin Kerbow authored Oct 28, 2019
  d11b93ec
- [AIX] Refactor AIX Call Lowering to use CCState. NFCI. · 582e3c09
  Sean Fertile authored Oct 28, 2019
  582e3c09
- Add Windows Control Flow Guard checks (/guard:cf). · d157a9bc
  Andrew Paverd authored Oct 28, 2019
  d157a9bc
- Precommit AArch64 test for -consider-local-interval-cost · 265ddc57
  Sanne Wouda authored Oct 28, 2019
  265ddc57
- [DAGCombiner] widen any_ext of popcount based on target support · 1ebd4a2e
  Sanjay Patel authored Oct 28, 2019
  1ebd4a2e
- [Codegen][ARM] Add float softening for cbrt · ba2c6255
  David Green authored Oct 23, 2019
  ba2c6255
- [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLE · f6e11a36
  vhscampos authored Oct 17, 2019
  f6e11a36
- [AArch64][SVE] Implement masked load intrinsics · da720a38
  Kerry McLaughlin authored Oct 28, 2019
  da720a38
- [RISCV] Lower llvm.trap and llvm.debugtrap · 7214f7a7
  Sam Elliott authored Oct 28, 2019
  7214f7a7