Commits · e5ed5e2cba20d395c9028a562a4f5a4dfc019c42 · Roger Ferrer / llvm-epi · GitLab

Apr 09, 2018
- [X86][MMX] Fix missing itinerary for PALIGNR · e5ed5e2c
  Simon Pilgrim authored Apr 09, 2018
  e5ed5e2c
- [X86][MMX] Fix missing itinerary for MOVQ2DQ instruction format · 140fee07
  Simon Pilgrim authored Apr 09, 2018
  140fee07
- [X86][MMX] Fix missing itinerary for CVTPI2PS · abf36113
  Simon Pilgrim authored Apr 09, 2018
  abf36113
- [AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32 · 2f8e146a
  Dmitry Preobrazhensky authored Apr 09, 2018
  2f8e146a
- [X86][MMX] Fix flipped reg/mem typo in MMX_MISC_FUNC_ITINS · 0047efdd
  Simon Pilgrim authored Apr 09, 2018
  0047efdd
- [X86][SSE] Fix f32 mul/div itinerary groups typo · 61312865
  Simon Pilgrim authored Apr 09, 2018
  61312865
- [NFC] fix trivial typos in comments and error message · 9ff2380e
  Hiroshi Inoue authored Apr 09, 2018
  9ff2380e
Apr 08, 2018
- [TargetSchedule] shrink interface for init(); NFCI · 0d7df36c
  Sanjay Patel authored Apr 08, 2018
  0d7df36c
- [X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs. · b7baa358
  Craig Topper authored Apr 08, 2018
  b7baa358
- [X86][Znver1] Remove InstRWs for BLENDVPS/PD · c362f42b
  Craig Topper authored Apr 08, 2018
  c362f42b
- [PowerPC] Change std::sort to llvm::sort in response to r327219 · 327fd5e4
  Mandeep Singh Grang authored Apr 08, 2018
  327fd5e4
- [X86] Change std::sort to llvm::sort in response to r327219 · 68a151a1
  Mandeep Singh Grang authored Apr 08, 2018
  68a151a1
- [X86][Btver2] Add vector extract costs · 86588fc8
  Simon Pilgrim authored Apr 08, 2018
  86588fc8
Apr 07, 2018
- [X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering. · ef37aebc
  Craig Topper authored Apr 07, 2018
  ef37aebc
- [CostModel][X86] Fix v32i16/v64i8 SETCC costs on AVX512BW targets · 80ce1dde
  Simon Pilgrim authored Apr 07, 2018
  80ce1dde
- Reapply ARM: Do not spill CSR to stack on entry to noreturn functions · e25e458d
  Tim Northover authored Apr 07, 2018
  e25e458d
- Revert "ARM: Do not spill CSR to stack on entry to noreturn functions" · de5f1965
  Vitaly Buka authored Apr 07, 2018
  de5f1965
- [NVPTX] add support for initializing fp16 arrays. · f256decd
  Artem Belevich authored Apr 06, 2018
  f256decd
Apr 06, 2018
- [NVPTX] Fixed vectorized LDG for f16. · a28e598e
  Artem Belevich authored Apr 06, 2018
  a28e598e
- [RISCV] Tablegen-driven Instruction Compression. · c1b0e66b
  Sameer AbuAsal authored Apr 06, 2018
  c1b0e66b
- [AMDGPU][MC][GFX9] Added s_call_b64 · ae31223b
  Dmitry Preobrazhensky authored Apr 06, 2018
  ae31223b
- [Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions · b7e54e84
  Krzysztof Parzyszek authored Apr 06, 2018
  b7e54e84
- [Hexagon] Prevent a stall across zero-latency instructions in a packet · aca8f327
  Krzysztof Parzyszek authored Apr 06, 2018
  aca8f327
- [Hexagon] Remove duplicated code, NFC · 269740a8
  Krzysztof Parzyszek authored Apr 06, 2018
  269740a8
- [Hexagon] Handle subregisters when calculating iteration count in HW loops · ed04f024
  Krzysztof Parzyszek authored Apr 06, 2018
  ed04f024
- [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done · 306b1a01
  Dmitry Preobrazhensky authored Apr 06, 2018
  306b1a01
- [X686] Add appropriate ReadAfterLd for the register input to memory forms of ADC/SBB. · c50570fb
  Craig Topper authored Apr 06, 2018
  c50570fb
- [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate* · f20aff56
  Dmitry Preobrazhensky authored Apr 06, 2018
  f20aff56
- [X86] Remove InstRWs for basic arithmetic instructions from Sandy Bridge scheduler model. · b9d298ec
  Craig Topper authored Apr 06, 2018
  b9d298ec
- [X86] Attempt to model basic arithmetic instructions in the... · f0d04261
  Craig Topper authored Apr 06, 2018
  f0d04261
- [X86] Add an extra store address cycle to WriteRMW in the Sandy... · f131b600
  Craig Topper authored Apr 06, 2018
  f131b600
- [X86] Merge itineraries for CLC, CMC, and STC. · 22d25a08
  Craig Topper authored Apr 06, 2018
  22d25a08
- [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions · 59399ae4
  Dmitry Preobrazhensky authored Apr 06, 2018
  59399ae4
- [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}. · b7b6e1da
  Pete Couperus authored Apr 06, 2018
  b7b6e1da
- [AMDGPU][MC][GFX9] Added s_dcache_discard* instructions · 4732d876
  Dmitry Preobrazhensky authored Apr 06, 2018
  4732d876
- [X86][SandyBridge] Add (V)DPPS memory fold latencies · 09eeb3a8
  Simon Pilgrim authored Apr 06, 2018
  09eeb3a8
- [X86][SandyBridge] SBWriteResPair +5cy Memory Folds · 8a83f16c
  Simon Pilgrim authored Apr 06, 2018
  8a83f16c
- [X86][SkylakeServer] Merge 2 InstRW entries to the same sched group. NFCI. · fd1f4fe5
  Simon Pilgrim authored Apr 06, 2018
  fd1f4fe5
- [PowerPC] allow D-form VSX load/store when accessing FrameIndex without offset · a2eefb6d
  Hiroshi Inoue authored Apr 06, 2018
  a2eefb6d
- Fix lld-x86_64-darwin13 build fails. · afb355bd
  Manoj Gupta authored Apr 05, 2018
  afb355bd