Commits · e6270395e33776e640a1eeeeda778f2b59234dc8 · Roger Ferrer / llvm-epi · GitLab

Nov 15, 2011
- Add vmov.f32 to materialize f32 immediate splats which cannot be handled by · 7ca4b6eb
  Evan Cheng authored Nov 15, 2011
  7ca4b6eb
- ARM VLDR/VSTR instructions don't need a size suffix. · 3e2c6f38
  Jim Grosbach authored Nov 14, 2011
  3e2c6f38
Nov 12, 2011
- Linear scan is going away. · 8ec1a92a
  Jakob Stoklund Olesen authored Nov 12, 2011
  8ec1a92a
- Switch a few tests off linearscan. · 4deff7bc
  Jakob Stoklund Olesen authored Nov 12, 2011
  4deff7bc
Sep 30, 2011
- ARM Darwin default relocation model is PIC. · 4e0dbee6
  Jim Grosbach authored Sep 30, 2011
  4e0dbee6
Sep 27, 2011
- Last batch of test conversions to new atomic instructions. · f6fbfd3f
  Eli Friedman authored Sep 27, 2011
  f6fbfd3f
Sep 26, 2011
- Convert more tests to new atomic instructions. · ab7b99ab
  Eli Friedman authored Sep 26, 2011
  ab7b99ab
Sep 13, 2011
- Generalize this test's CHECK statements to handle different indvars modes. · 1191773a
  Andrew Trick authored Sep 13, 2011
  1191773a
Aug 30, 2011
- Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical · e891654a
  Evan Cheng authored Aug 30, 2011
  e891654a
Aug 20, 2011
- Update tests. · 066e9ec1
  Jim Grosbach authored Aug 19, 2011
  066e9ec1
Aug 18, 2011
- Thumb assembly parsing and encoding for LDM instruction. · 90103ccc
  Jim Grosbach authored Aug 18, 2011
  90103ccc
Aug 08, 2011
- Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly... · a27da989
  Eli Friedman authored Aug 08, 2011
  a27da989
Aug 04, 2011
- Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. · 15e5b742
  Jakub Staszak authored Aug 03, 2011
  15e5b742
Jul 19, 2011
- Introduce MCCodeGenInfo, which keeps information that can affect codegen · 2129f596
  Evan Cheng authored Jul 19, 2011
  2129f596
Jul 13, 2011
- Improve codegen for select's: · f863e3fb
  Evan Cheng authored Jul 13, 2011
  f863e3fb
Jul 12, 2011
- Improve test cases from r134746. · ade1fb17
  Jim Grosbach authored Jul 12, 2011
  ade1fb17
Jul 08, 2011
- Make tBX_RET and tBX_RET_vararg predicable. · 7471937a
  Jim Grosbach authored Jul 08, 2011
  7471937a
- Fix more register allocation sensitive tests. · bbe2a5cf
  Jakob Stoklund Olesen authored Jul 08, 2011
  bbe2a5cf
Jul 07, 2011
- Change some ARM subtarget features to be single bit yes/no in order to sink... · 8b2bda09
  Evan Cheng authored Jul 07, 2011
  8b2bda09
Jul 02, 2011
- FileCheck-ize another test. Reduces the llc invocations from 8 to 1, and · a6e593b4
  Chandler Carruth authored Jul 02, 2011
  a6e593b4
Jul 01, 2011
- ARMv7M vs. ARMv7E-M support. · cf1464d9
  Jim Grosbach authored Jul 01, 2011
  cf1464d9
- Thumb1 register to register MOV instruction is predicable. · b98ab91e
  Jim Grosbach authored Jun 30, 2011
  b98ab91e
Jun 30, 2011
- Pseudo-ize the t2LDMIA_RET instruction. · 353da731
  Jim Grosbach authored Jun 30, 2011
  353da731
Jun 29, 2011
- Don't depend on the optimization reverted in r134067. · d2a84f6a
  Benjamin Kramer authored Jun 29, 2011
  d2a84f6a
Jun 19, 2011
- Remove support for parsing the "type i32" syntax for defining a numbered · 8936d2bf
  Chris Lattner authored Jun 19, 2011
  8936d2bf
Jun 18, 2011
- rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which is · 80ed9dc9
  Chris Lattner authored Jun 18, 2011
  80ed9dc9
- Switch ARM to using AltOrders instead of MethodBodies. · 831ae010
  Jakob Stoklund Olesen authored Jun 18, 2011
  831ae010
Jun 17, 2011
- manually upgrade a bunch of tests to modern syntax, and remove some that · b90ed223
  Chris Lattner authored Jun 17, 2011
  b90ed223
Jun 14, 2011
- Implement Jakob's suggestion on how to detect fall thought without calling · 844485af
  Rafael Espindola authored Jun 14, 2011
  844485af
Jun 12, 2011
- AnalyzeBranch doesn't change which successors a bb has, just the order · defd4b08
  Rafael Espindola authored Jun 12, 2011
  defd4b08
Jun 08, 2011
- Fix an issue where the two-address conversion pass incorrectly rewrites untied · 2e252de5
  Cameron Zwarich authored Jun 07, 2011
  2e252de5
Jun 03, 2011
- Switch AllocationOrder to using RegisterClassInfo instead of a BitVector · b8bf3c0f
  Jakob Stoklund Olesen authored Jun 03, 2011
  b8bf3c0f
May 13, 2011
- Since I can't reproduce the failures from 131261, re-trying with a · aa02c084
  Stuart Hastings authored May 13, 2011
  aa02c084
- Revert 131266 and 131261 due to buildbot complaints. · 8d57d8ea
  Stuart Hastings authored May 13, 2011
  8d57d8ea
- Tweak 131261 (thumb2-cbnz.ll) to generate the intended cbnz. · ef494025
  Stuart Hastings authored May 13, 2011
  ef494025
- Non-fast-isel followup to 129634; correctly handle branches controlled · 89f1b47e
  Stuart Hastings authored May 12, 2011
  89f1b47e
May 06, 2011
- Re-revert r130877; it's apparently causing a regression on 197.parser, · 54019626
  Eli Friedman authored May 06, 2011
  54019626
May 05, 2011
- Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases. · 0fe4608a
  Eli Friedman authored May 04, 2011
  0fe4608a
May 04, 2011
- Back out r130862; it appears to be breaking bootstrap. · 3bd79ba8
  Eli Friedman authored May 04, 2011
  3bd79ba8
- Teach MachineCSE how to do simple cross-block CSE involving physregs. This... · a16fc2fe
  Eli Friedman authored May 04, 2011
  a16fc2fe