Commits · e638d8b2bc27d620ea26fcc730f7cba29ab82349 · Roger Ferrer / llvm-epi · GitLab

Mar 04, 2021
- [X86][CodeGenPrepare] Try to reuse IV's incremented value instead of adding the offset, part 1 · d9e93e8e
  Max Kazantsev authored Mar 04, 2021
  d9e93e8e
- Add the use of register r for outlined function when register r is live in and defined later. · 7c2192b2
  Jin Lin authored Mar 03, 2021
  7c2192b2
Mar 03, 2021
- [AArch64] Add implicit uses for operands when expanding BLR_RVMARKER. · 75805dce
  Florian Hahn authored Mar 03, 2021
  75805dce
- [SystemZ] Reimplement the i8/i16 compare-and-swap logic. · 7334b3dc
  Jonas Paulsson authored Feb 26, 2021
  7334b3dc
- [VirtRegRewriter] Insert missing killed flags when tracking subregister liveness · 54c0f520
  Baptiste Saleil authored Mar 03, 2021
  54c0f520
- [X86] Fold scalar_to_vector(x) -> extract_subvector(broadcast(x),0) iff broadcast(x) exists · aa4afebb
  Simon Pilgrim authored Mar 03, 2021
  aa4afebb
- Revert "[ObjC][ARC] Use operand bundle 'clang.arc.attachedcall' instead of... · 0a5dd067
  Hans Wennborg authored Mar 03, 2021
  0a5dd067
- [AVR] Fix def state of operands · 15f495c0
  Ayke van Laethem authored Feb 21, 2021
  15f495c0
- [AVR] Fix expansion of NEGW · bbfef8ac
  Ayke van Laethem authored Feb 21, 2021
  bbfef8ac
- GlobalISel: Add default implementation of assignValueToReg · 78dcff48
  Matt Arsenault authored Mar 02, 2021
  78dcff48
- [AMDGPU] Introduce Strict WQM mode · 4672bac1
  Piotr Sobczak authored Mar 03, 2021
  4672bac1
- [AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm · c3ce7bae
  Piotr Sobczak authored Mar 02, 2021
  c3ce7bae
- [AMDGPU] Rename llvm.amdgcn.msaa.load to llvm.amdgcn.msaa.load.x · 2ddac69f
  Carl Ritson authored Mar 03, 2021
  2ddac69f
- [ARM] Ensure undef is propagated to CBZ/CBNZ flags · ab280cba
  David Green authored Mar 03, 2021
  ab280cba
- [WebAssembly] Swap operand order of call_indirect in text format · 4307069d
  Andy Wingo authored Mar 02, 2021
  4307069d
- [PowerPC] Allow spilling GPR to VSR on AIX · 72d4a41b
  Qiu Chaofan authored Mar 03, 2021
  72d4a41b
- [LegalizeVectorTypes] Improve SplitVecRes_INSERT_SUBVECTOR to handle subvector... · 543b901e
  Craig Topper authored Mar 02, 2021
  543b901e
- [AIX][TLS] Generate TLS variables in assembly files · 1756b2ad
  Victor Huang authored Mar 02, 2021
  1756b2ad
- [test] Fix CodeGen/VE/Scalar tests · 1e46b6f4
  Fangrui Song authored Mar 02, 2021
  
  1e46b6f4
Mar 02, 2021
- GlobalISel: Merge and cleanup more AMDGPU call lowering code · fd82cbcf
  Matt Arsenault authored Feb 09, 2021
  fd82cbcf
- [WebAssembly] Fix more ExceptionInfo grouping bugs · 4a58116b
  Heejin Ahn authored Feb 27, 2021
  4a58116b
- BPF: Fix a bug in peephole TRUNC elimination optimization · 51cdb780
  Yonghong Song authored Mar 02, 2021
  51cdb780
- [AArch64][GlobalISel] Enable use of the optsize predicate in the selector. · 8a316045
  Amara Emerson authored Feb 24, 2021
  8a316045
- [SDAG] allow partial undef vector constants with select->logic folds · 415c67ba
  Sanjay Patel authored Mar 02, 2021
  415c67ba
- [AArch64] add select tests with partial vector undefs; NFC · 1b5ab135
  Sanjay Patel authored Mar 02, 2021
  
  1b5ab135
- [SystemZ] Assign the full space for promoted and split outgoing args. · 52bbbf4d
  Jonas Paulsson authored Feb 25, 2021
  52bbbf4d
- [RISCV] Support fixed-length INSERT_VECTOR_ELT · c1695ddf
  Fraser Cormack authored Mar 01, 2021
  c1695ddf
- [SDAG] allow vector types for select->logic folds · 7fce3322
  Sanjay Patel authored Mar 02, 2021
  7fce3322
- [RISCV] Lower CONCAT_VECTORS to INSERT_SUBVECTOR nodes · de2b7001
  Fraser Cormack authored Mar 01, 2021
  de2b7001
- Revert "[X86] Fold shuffle(not(x),undef) -> not(shuffle(x,undef))" · 10c256cc
  Benjamin Kramer authored Mar 02, 2021
  10c256cc
- [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P · 28f164bc
  Dmitry Preobrazhensky authored Mar 02, 2021
  28f164bc
- [AArch64] Mark test depending on -debug as requiring asserts · 1e34cb00
  Benjamin Kramer authored Mar 02, 2021
  
  1e34cb00
- [ARM] Add handling of t2LDRSB/t2LDRSH in Constant Island Pass · d6ba8ecb
  David Green authored Mar 02, 2021
  d6ba8ecb
- [AMDGPU] Do not check max-bb for a single block callee · 7c724a89
  Stanislav Mekhanoshin authored Mar 01, 2021
  7c724a89
- [Diagnose] Unify MCContext and LLVMContext diagnosing · 5de2d189
  Yuanfang Chen authored Feb 23, 2021
  5de2d189
Mar 01, 2021
- [GlobalISel] Bail on G_PHI narrowing of odd types (PR48188) · c35761db
  Nikita Popov authored Mar 01, 2021
  c35761db
- [AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the · b783aa89
  Amara Emerson authored Feb 26, 2021
  b783aa89
- [ARM] Update and add extra WLS testing. NFC · 54e28761
  David Green authored Mar 01, 2021
  
  54e28761
- [AArch64] add tests for select-of-bools; NFC · fd64580f
  Sanjay Patel authored Mar 01, 2021
  
  fd64580f
- [x86] add tests for select-of-bools; NFC · bcd504d8
  Sanjay Patel authored Mar 01, 2021
  
  bcd504d8