Commits · e660fdd953b494f6b4f6b41782a47a5eb367b333 · Roger Ferrer / llvm-epi · GitLab

Jan 23, 2012
- Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] · e660fdd9
  Devang Patel authored Jan 23, 2012
  e660fdd9
- Simplify some NEON assembly pseudo definitions. · d28ef9ac
  Jim Grosbach authored Jan 23, 2012
  d28ef9ac
- Intel syntax: Parse segment registers. · 880bc164
  Devang Patel authored Jan 23, 2012
  880bc164
- ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here. · 28ea8f52
  NAKAMURA Takumi authored Jan 23, 2012
  28ea8f52
- Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. · edd1d0ac
  Craig Topper authored Jan 23, 2012
  edd1d0ac
- An option to selectively enable parts of ARM EHABI support. · 482cdc4e
  Evgeniy Stepanov authored Jan 23, 2012
  482cdc4e
- Update more places to use target specific nodes for vector shifts instead of intrinsics. · 6b90c5d0
  Craig Topper authored Jan 23, 2012
  6b90c5d0
- Custom lower vector shift intrinsics to target specific nodes and remove the... · 5e80db4e
  Craig Topper authored Jan 23, 2012
  5e80db4e
- Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32... · 20c98df3
  Craig Topper authored Jan 23, 2012
  20c98df3
- Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. · 0b7ad76b
  Craig Topper authored Jan 22, 2012
  0b7ad76b
Jan 22, 2012
- Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86... · bd488437
  Craig Topper authored Jan 22, 2012
  bd488437
- Use Attributes::None instead of 0 after r148553 change on Attributes from... · e197d943
  Nicolas Geoffray authored Jan 22, 2012
  e197d943
- Add target specific ISD node types for SSE/AVX vector shuffle instructions and... · 09462641
  Craig Topper authored Jan 22, 2012
  09462641
- Add fused multiple+add instructions from VFPv4. · 5482b9f5
  Anton Korobeynikov authored Jan 22, 2012
  5482b9f5
- Make code a little less verbose. · a4ed5246
  Craig Topper authored Jan 22, 2012
  a4ed5246
- Remove unused X86 ISD node type defines. · cb3433cd
  Craig Topper authored Jan 22, 2012
  cb3433cd
- Move some vector shift patterns into their instruction definitions. · 123adfa0
  Craig Topper authored Jan 22, 2012
  123adfa0
Jan 21, 2012
- Add memory patterns for some of the fp<->integer conversion instructions. Fold... · dcaa5fbd
  Craig Topper authored Jan 21, 2012
  dcaa5fbd
- Remove unused variables. · 5cff13a3
  Benjamin Kramer authored Jan 21, 2012
  5cff13a3
- Fix PR11819 introduced by r148537. I'd commit the test case, but the generated... · 39bc1e4d
  Craig Topper authored Jan 21, 2012
  39bc1e4d
- Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction. · 78dcaed8
  Jim Grosbach authored Jan 21, 2012
  78dcaed8
Jan 20, 2012
- Intel syntax: Robustify register parsing. · ce6a2ca8
  Devang Patel authored Jan 20, 2012
  ce6a2ca8
- More dead code removal (using -Wunreachable-code) · 46a9f016
  David Blaikie authored Jan 20, 2012
  46a9f016
- Intel syntax: Parse ... PTR [-8] · d0930fff
  Devang Patel authored Jan 20, 2012
  d0930fff
- Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. · f36613cb
  Devang Patel authored Jan 20, 2012
  f36613cb
- ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651 > · 6c7aaec0
  Bob Wilson authored Jan 20, 2012
  6c7aaec0
- VST2 four-register w/ update pseudos for fixed/register update. · 90f5780f
  Jim Grosbach authored Jan 20, 2012
  90f5780f
- NEON use vmov.i32 to splat some f32 values into vectors. · a9d36fbc
  Jim Grosbach authored Jan 20, 2012
  a9d36fbc
- Remove a bunch of unused variable assignments. · 084b9f41
  Benjamin Kramer authored Jan 20, 2012
  084b9f41
- Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As... · a4094790
  Craig Topper authored Jan 20, 2012
  a4094790
- Add support for selecting 256-bit PALIGNR. · 3469212c
  Craig Topper authored Jan 20, 2012
  3469212c
- Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. · 32c7c25d
  Eli Friedman authored Jan 20, 2012
  32c7c25d
Jan 19, 2012
- Silence warnings about mixing enums. · 116e99a4
  Benjamin Kramer authored Jan 19, 2012
  116e99a4
- Post process 'and', 'sub' instructions and select better encoding, if available. · f83dcfd0
  Devang Patel authored Jan 19, 2012
  f83dcfd0
- Intel syntax: There is no need to create unary expr for simple negative displacement. · 2529dd9e
  Devang Patel authored Jan 19, 2012
  2529dd9e
- Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. · 4a62ff9b
  Devang Patel authored Jan 19, 2012
  4a62ff9b
- Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. · 4c7eb477
  Evgeniy Stepanov authored Jan 19, 2012
  4c7eb477
- Folding table additions and fixes for AVX. · a875b7cc
  Craig Topper authored Jan 19, 2012
  a875b7cc
- Merge 128-bit and 256-bit SHUFPS/SHUFPD handling. · 80576e8d
  Craig Topper authored Jan 19, 2012
  80576e8d
- ARM assembly diagnostic caret in better position for FPImm. · 235c8d2d
  Jim Grosbach authored Jan 19, 2012
  235c8d2d