Commits · e7b920e6fe7c961724cc5bce0c5ffd3d41885cf4 · Roger Ferrer / llvm-epi · GitLab

Jun 12, 2020
- [DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2)) · e7b920e6
  Michael Liao authored Jun 04, 2020
  e7b920e6
- [AArch64][GlobalISel] Allow G_DUP for elements smaller than 32 B. · d3a56f06
  Jessica Paquette authored Jun 05, 2020
  d3a56f06
- [AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes · 305862a5
  Jessica Paquette authored Jun 09, 2020
  305862a5
- GlobalISel: Fix not erasing old instruction in sitofp/uitofp lowering · 350ee7fb
  Matt Arsenault authored Jun 12, 2020
  
  350ee7fb
- DAGCombiner optimization for pow(x,0.75) and pow(x,0.25) on double and single... · 2d038370
  Masoud Ataei authored Jun 12, 2020
  2d038370
- [DAG] foldAddSubOfSignBit - add support for non-uniform vector constants · 5509e2cc
  Simon Pilgrim authored Jun 12, 2020
  
  5509e2cc
- [X86] Add non-uniform vector signbit test cases · a5a00155
  Simon Pilgrim authored Jun 12, 2020
  
  a5a00155
- [X86][SSE] combineX86ShuffleChain - combine INSERT_VECTOR_ELT patterns to INSERTPS · 8d30945a
  Simon Pilgrim authored Jun 12, 2020
  8d30945a
- [BreakCritEdges] Add option to opt-out of perserving loop-simplify. · 4495a6b1
  Florian Hahn authored Jun 12, 2020
  4495a6b1
- [ObjectYAML][test] Use a single test file to test the empty 'DWARF' entry. · 7e0827e8
  Xing GUO authored Jun 12, 2020
  7e0827e8
- [VPlan] Reject loops without computable backedge taken counts · 3a846d4d
  Florian Hahn authored Jun 12, 2020
  3a846d4d
- [AMDGPU] Add G16 support to image instructions · 29a6ad94
  Sebastian Neubauer authored Mar 25, 2020
  29a6ad94
- [yaml2obj][MachO] - Fix PubName/PubType handling. · d95f8e7a
  Georgii Rymar authored Jun 11, 2020
  d95f8e7a
- [InstCombine] "X - (X / C) * C == 0" to "X & C-1 == 0" · 012909dc
  EgorBo authored Jun 12, 2020
  012909dc
- [NFC][InstCombine] Tests for "X - (X / C) * C == 0" pattern · 6538b3ad
  EgorBo authored Jun 12, 2020
  6538b3ad
- [AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions. · c35ed40f
  Kristof Beyls authored Jun 11, 2020
  c35ed40f
- [StackSafety] Fix byval handling · 99930732
  Vitaly Buka authored Jun 11, 2020
  99930732
- [llvm-objcopy][MachO] Fix cmdsize of LC_RPATH · c966ed8d
  Alexander Shaposhnikov authored Jun 11, 2020
  c966ed8d
- [BPF] fix incorrect type in BPFISelDAGToDAG readonly load optimization · 4db18781
  Yonghong Song authored Jun 10, 2020
  4db18781
- Revert "[PowerPC][NFC] Testing ROTL of v1i128." · af9f8c24
  Esme-Yi authored Jun 12, 2020
  af9f8c24
- [llvm][llvm-nm] add TextAPI/MachO support · 28fefcc8
  Cyndy Ishida authored Jun 11, 2020
  28fefcc8
- Verify MemorySSA after all updates. · 519b019a
  Alina Sbirlea authored Jun 11, 2020
  519b019a
- AMDGPU/GlobalISel: Fix select of private <2 x s16> load · 7d913bec
  Matt Arsenault authored Jun 11, 2020
  
  7d913bec
- AMDGPU/GlobalISel: Fix select of <8 x s64> scalar load · 27f8bd94
  Matt Arsenault authored Jun 11, 2020
  
  27f8bd94
- AMDGPU/GlobalISel: Set insert point when emitting control flow pseudos · 2247072b
  Matt Arsenault authored Jun 11, 2020
  2247072b
- [InlineCost] Preparational patch for creation of Printer pass. · 1022b5eb
  Kirill Naumov authored Jun 11, 2020
  1022b5eb
- Fixed assertion in SROA if block has ho successors · a98d618f
  Stanislav Mekhanoshin authored Jun 11, 2020
  a98d618f
- [WebAssembly] Make BR_TABLE non-duplicable · c5d01234
  Thomas Lively authored Jun 11, 2020
  c5d01234
Jun 11, 2020
- [GlobalISel][test] Add REQUIRES: asserts after D76934 · 432f20bc
  Fangrui Song authored Jun 11, 2020
  
  432f20bc
- [X86] Force VIA PadLock crypto instructions to emit a 0xF3 prefix when they... · 8fa3e8fa
  Craig Topper authored Jun 11, 2020
  8fa3e8fa
- [AArch64] Regenerate SVE test llvm-ir-to-intrinsic.ll. · 12459ec9
  Eli Friedman authored Jun 11, 2020
  
  12459ec9
- Regenerated SROA phi-gep.ll test. NFC. · 59491b20
  Stanislav Mekhanoshin authored Jun 11, 2020
  
  59491b20
- [VectorCombine] add tests for compare scalarization; NFC · d386297c
  Sanjay Patel authored Jun 10, 2020
  
  d386297c
- AMDGPU/GlobalISel: Fix lower for f64->f16 G_FPTRUNC · bd3d951b
  Petar Avramovic authored Jun 11, 2020
  bd3d951b
- [llvm-objdump] Decrease instruction indentation for non-x86 · 5ee57173
  Fangrui Song authored Jun 11, 2020
  5ee57173
- [X86] Fold vXi1 OR(KSHIFTL(X,NumElts/2),Y) -> KUNPCK · 7706c7af
  Simon Pilgrim authored Jun 11, 2020
  7706c7af
- [IR] Clean up dead instructions after simplifying a conditional branch · 69bdfb07
  Jay Foad authored May 18, 2020
  69bdfb07
- [IR] Remove assert from ShuffleVectorInst · 3d5f7c85
  Sam Parker authored Jun 11, 2020
  3d5f7c85
- Revert "[IR] Clean up dead instructions after simplifying a conditional branch" · f45c65aa
  Jay Foad authored Jun 11, 2020
  f45c65aa
- [X86][AVX512] Add second test case for PR32547 · 8824913e
  Simon Pilgrim authored Jun 11, 2020
  8824913e