Commits · e83591c6160318841f89342dbf9f119616202a13 · Roger Ferrer / llvm-epi · GitLab

Mar 28, 2010
- the FPCmp node returns an i32. · e83591c6
  Chris Lattner authored Mar 28, 2010
  e83591c6
- fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest · ec5fe658
  Chris Lattner authored Mar 28, 2010
  ec5fe658
Mar 27, 2010
- Fix indentation. · 0f8a0283
  Bob Wilson authored Mar 27, 2010
  0f8a0283
- Add a format argument to the N3V and N3VX classes, removing the N3Vf class. · cf603fb1
  Bob Wilson authored Mar 27, 2010
  cf603fb1
- eliminate the last of the parallel's! · 07943af5
  Chris Lattner authored Mar 27, 2010
  07943af5
- Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set · 6094cdab
  Johnny Chen authored Mar 27, 2010
  6094cdab
- eliminate almost all the rest of the x86-32 parallels. · c5e20d90
  Chris Lattner authored Mar 27, 2010
  c5e20d90
- Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass · 44313db5
  Jim Grosbach authored Mar 27, 2010
  44313db5
- Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified · 93acfbf4
  Johnny Chen authored Mar 26, 2010
  93acfbf4
Mar 26, 2010
- Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8} · 0b57de3c
  Johnny Chen authored Mar 26, 2010
  0b57de3c
- Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not · 2cf04957
  Johnny Chen authored Mar 26, 2010
  2cf04957
- vldm/vstm can only do up to 16 double-word registers at a time. · bf59859b
  Jim Grosbach authored Mar 26, 2010
  bf59859b
- Add N3RegFrm to represent "NEON 3 vector register format" instructions. · 8fc94d63
  Johnny Chen authored Mar 26, 2010
  8fc94d63
- Do not sibcall if stack needs to be dynamically aligned. · 3365fb14
  Evan Cheng authored Mar 26, 2010
  3365fb14
- Allow trivial sibcall of vararg callee when no arguments are being passed. · 00a620c6
  Evan Cheng authored Mar 26, 2010
  00a620c6
- Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily · 5d4e917d
  Johnny Chen authored Mar 26, 2010
  5d4e917d
- switch the flag for using NEON for SP floating point to a subtarget 'feature'. · 71fcb4fe
  Jim Grosbach authored Mar 25, 2010
  71fcb4fe
- need to fix 'make check' tests first. revert for a moment. · 42bb89c7
  Jim Grosbach authored Mar 25, 2010
  42bb89c7
- switch the flag for using NEON for SP floating point to a subtarget 'feature' · 7fce4e39
  Jim Grosbach authored Mar 25, 2010
  7fce4e39
- Removed instruction class NI from ARMInstrFormats.td. · a3617ec8
  Johnny Chen authored Mar 25, 2010
  a3617ec8
- switch the use-vml[as] instructions flag to a subtarget 'feature' · a43386ba
  Jim Grosbach authored Mar 25, 2010
  a43386ba
Mar 25, 2010
- Add NVDupLnFrm and change NVDupLane class to use that format. · 91d27744
  Johnny Chen authored Mar 25, 2010
  91d27744
- ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu · 4b3b2ef6
  Jim Grosbach authored Mar 25, 2010
  4b3b2ef6
- Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to · d82f9002
  Johnny Chen authored Mar 25, 2010
  d82f9002
- Fix -Asserts warning, again. · d919276b
  Daniel Dunbar authored Mar 25, 2010
  d919276b
- Tag SSE2 integer instructions as SSEPackedInt. · 3758ff91
  Jakob Stoklund Olesen authored Mar 25, 2010
  3758ff91
- Teach TableGen to understand X.Y notation in the TSFlagsFields strings. · f8d7eda6
  Jakob Stoklund Olesen authored Mar 25, 2010
  f8d7eda6
- Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. · 49e121d5
  Jakob Stoklund Olesen authored Mar 25, 2010
  49e121d5
- Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ, · 45ab3f3c
  Johnny Chen authored Mar 25, 2010
  45ab3f3c
- Reapply Kevin's change 94440, now that Chris has fixed the limitation on · e543e7fc
  Bob Wilson authored Mar 25, 2010
  e543e7fc
- eliminate a bunch more parallels now that scheduling · 23bf99a9
  Chris Lattner authored Mar 25, 2010
  23bf99a9
- Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this: · b07a29ec
  Evan Cheng authored Mar 25, 2010
  b07a29ec
- Speculatively revert this to see if it fixes buildbot failures. · 5b2da69f
  Bob Wilson authored Mar 24, 2010
  5b2da69f
Mar 24, 2010
- Added the Advanced Encryption Standard (AES) Instructions. · f5584a73
  Kevin Enderby authored Mar 24, 2010
  f5584a73
- Make the use of the vmla and vmls VFP instructions controllable via cmd line. · 34de7768
  Jim Grosbach authored Mar 24, 2010
  34de7768
- Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does · b96eb684
  Kevin Enderby authored Mar 24, 2010
  b96eb684
- Per chris's request, add some comments. · 2ceb2884
  Nate Begeman authored Mar 24, 2010
  2ceb2884
- Trivial formating change. · bff23ca6
  Johnny Chen authored Mar 24, 2010
  bff23ca6
- BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts. · 583e05d8
  Nate Begeman authored Mar 24, 2010
  583e05d8
- Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. · e99953ce
  Johnny Chen authored Mar 24, 2010
  e99953ce