Commits · ea2cdbf5e655ce157c2224f7d427229be55551cc · Roger Ferrer / llvm-epi · GitLab

Sep 02, 2021
- [DAGCombine] Add node level checks for fp-contract and fp-ninf in... · 0baace53
  Abinav Puthan Purayil authored Aug 02, 2021
  0baace53
- [AArch64][test] Add new tests for (mul (add x, c0), c1) · 14500628
  Ben Shi authored Aug 27, 2021
  14500628
- Revert "[AArch64][GlobalISel] Legalize bswap <2 x i16>" · 9237eda3
  Jon Roelofs authored Sep 01, 2021
  9237eda3
- [AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr · f3645c79
  Stanislav Mekhanoshin authored Sep 01, 2021
  f3645c79
- [AMDGPU] Introduce optimizeCompareInstr · bf77b112
  Stanislav Mekhanoshin authored Aug 31, 2021
  bf77b112
Sep 01, 2021
- [Codegen][TLI][X86] SimplifyMultipleUseDemandedBits(): 0'th vec subreg... · f5753125
  Roman Lebedev authored Sep 02, 2021
  f5753125
- [ARM] Add MVE lowering for fptosi.sat · 49476a4d
  David Green authored Sep 01, 2021
  49476a4d
- [AMDGPU] enable scalar compare in truncate selection · e3cbf1d4
  alex-t authored Sep 01, 2021
  e3cbf1d4
- [WebAssembly] Support opaque pointers in FixFunctionBitcasts · 7f058ce8
  Nikita Popov authored Aug 28, 2021
  7f058ce8
- [RISCV] Fold (RISCVISD::SELECT_CC X, Y, CC, Z, Z) -> Z. · ccbb4c8b
  Craig Topper authored Sep 01, 2021
  ccbb4c8b
- [RISCV] Add a test case showing an extra sext.w near a sh2add with multiple uses. NFC · af1ca435
  Craig Topper authored Sep 01, 2021
  af1ca435
- [WebAssembly] Lower v2f32 to v2f64 extending loads with promote_low · fec47492
  Thomas Lively authored Sep 01, 2021
  fec47492
- [AArch64][GlobalISel] Handle any-extending FPR loads in manual selection code. · a86bbe1e
  Amara Emerson authored Aug 31, 2021
  a86bbe1e
- Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" · 97688bfd
  hsmahesha authored Sep 01, 2021
  97688bfd
- Revert "Disable ReplaceLDS pass, patch up tests to match" · 5ae6804d
  hsmahesha authored Sep 01, 2021
  5ae6804d
- [PowerPC] Implement quadword atomic load/store · 5eaebd5d
  Kai Luo authored Sep 01, 2021
  5eaebd5d
- [AMDGPU] Split entry basic block after alloca instructions. · 98f47131
  hsmahesha authored Sep 01, 2021
  98f47131
- [X86] Enable half type support in inline assembly constraints · 74043cae
  Wang, Pengfei authored Sep 01, 2021
  74043cae
Aug 31, 2021
- [RegAlloc] Immediately delete dead instructions with live uses · d170945b
  Stanislav Mekhanoshin authored Aug 30, 2021
  d170945b
- Moved the test to X86 as it's x86 specific. · 1d369883
  Chih-Ping Chen authored Aug 30, 2021
  
  1d369883
- [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() · e9b3f257
  Nick Desaulniers authored Aug 31, 2021
  e9b3f257
- [PPCISelLowering] avoid emitting libcalls to __mulodi4() · d8b6ae07
  Nick Desaulniers authored Aug 31, 2021
  d8b6ae07
- [AMDGPU] Enable ds_min/ds_max on more subtargets · c9683926
  Joe Nash authored Aug 31, 2021
  c9683926
- [GlobalISel] Don't use G_FPTOSI in G_ISNAN legalization · 94d3ff09
  Jessica Paquette authored Aug 31, 2021
  94d3ff09
- [ARM] Add missing validForTailPredication for VMINNM/VMAXNM · 22c38412
  David Green authored Aug 31, 2021
  22c38412
- [ARM] Test for VMINNM/VMAXNM in tail predicated loops. · 198259be
  David Green authored Aug 31, 2021
  
  198259be
- Make a generic test generic again. · 71fbfd4e
  Paul Robinson authored Aug 31, 2021
  71fbfd4e
- Fix test by adding REQUIRES: x86-registered-target to skip test in... · 76a1a415
  Douglas Yung authored Aug 31, 2021
  76a1a415
- [WebAssembly] Free setjmpTable before exiting calls in EmSjLj · 3419e85b
  Heejin Ahn authored Aug 30, 2021
  3419e85b
- [WebAssembly] Share rethrowing BBs in LowerEmscriptenEHSjLj · b8fc71b7
  Heejin Ahn authored Aug 27, 2021
  b8fc71b7
Aug 30, 2021
- [COFF] Force Symbols containing '.' to be quoted · ea853911
  Keno Fischer authored Aug 19, 2021
  ea853911
- [LegalizeTypes][X86] Improve ExpandIntRes_FP_TO_SINT/ExpandIntRes_FP_TO_UINT... · 201f6446
  Craig Topper authored Aug 30, 2021
  201f6446
- [SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero · 789f0128
  Bjorn Pettersson authored Aug 30, 2021
  789f0128
- Teach the AArch64 backend patterns to generate the EOR3 instruction. · db9de22f
  Owen Anderson authored Aug 26, 2021
  db9de22f
- [DebugInfo] Remove the restriction on the size of DIStringType · 070090cf
  Chih-Ping Chen authored Aug 30, 2021
  070090cf
- [DIBuilder] Do not replace empty enum types · 47b239eb
  Ellis Hoag authored Aug 30, 2021
  47b239eb
- [RISCV] Enable CONCAT_VECTORS for fixed FP vectors. · 0560a4ad
  Craig Topper authored Aug 30, 2021
  0560a4ad
- [DAGCombiner][RISCV] Don't use vector types in... · 705d0057
  Craig Topper authored Aug 30, 2021
  705d0057
- [X86] AVX512FP16 instructions enabling 6/6 · ab40dbfe
  Wang, Pengfei authored Aug 30, 2021
  ab40dbfe
- [PowerPC] Set branch/call instructions as no hasSideEffects · 3bdd850d
  Qiu Chaofan authored Aug 30, 2021
  3bdd850d