Commits · ea91cca593bb543edce86c15c2948ef71b022932 · Roger Ferrer / llvm-epi · GitLab

Nov 15, 2016
- [AMDGPU] Add wave barrier builtin · ea91cca5
  Stanislav Mekhanoshin authored Nov 15, 2016
  ea91cca5
- [x86] auto-generate checks; NFC · 22465125
  Sanjay Patel authored Nov 15, 2016
  22465125
- [LSR] Allow formula containing Reg for SCEVAddRecExpr related with outerloop. · 7ccf7651
  Wei Mi authored Nov 15, 2016
  7ccf7651
- Integer legalization: fix MUL expansion · c3f6c97f
  Pawel Bylica authored Nov 15, 2016
  c3f6c97f
- vector load store with length (left justified) llvm portion · a19c9e60
  Zaara Syeda authored Nov 15, 2016
  a19c9e60
- [X86][SSE] Improve SINT_TO_FP of boolean vector results (signum) · ceffb43b
  Simon Pilgrim authored Nov 15, 2016
  ceffb43b
- [PowerPC] Implement BE VSX load/store builtins - llvm portion. · 5f850cd1
  Tony Jiang authored Nov 15, 2016
  5f850cd1
- [X86][FastISel] Fix lowering of overflow result on AVX512 targets · f0b9b57b
  Zvi Rackover authored Nov 15, 2016
  f0b9b57b
- [ARM] Add machine scheduler for Cortex-R52 · f043dac2
  Javed Absar authored Nov 15, 2016
  f043dac2
- DAGCombiner: fix combine of trunc and select · b5735534
  Asaf Badouh authored Nov 15, 2016
  b5735534
- [X86][GlobalISel] Add minimal call lowering support to the IRTranslator · 76dbf265
  Zvi Rackover authored Nov 15, 2016
  76dbf265
- [AVX-512] Add an example test case for PR31018. · 0637099f
  Craig Topper authored Nov 15, 2016
  0637099f
- AMDGPU: Fix f16 fabs/fneg · c79dc70d
  Matt Arsenault authored Nov 15, 2016
  c79dc70d
- AMDGPU: Fix formatting of 1/2pi immediate · 972034bd
  Matt Arsenault authored Nov 15, 2016
  972034bd
- MIRParser: Add support for parsing vreg reg alloc hints · 9c884e49
  Tom Stellard authored Nov 15, 2016
  9c884e49
- [AArch64] Compute the Newton series for reciprocals natively · 9fc54826
  Evandro Menezes authored Nov 14, 2016
  9fc54826
Nov 14, 2016
- GlobalISel: add tests for G_ZEXT/G_SEXT to types smaller than 32-bits. · e33b1754
  Tim Northover authored Nov 14, 2016
  e33b1754
- RegAllocGreedy: Properly initialize this pass, so that -run-pass will work · 11e60ff7
  Tom Stellard authored Nov 14, 2016
  11e60ff7
- Recommit: ARM: sort register lists by encoding in push/pop instructions. · 46a6f0fb
  Tim Northover authored Nov 14, 2016
  46a6f0fb
- [X86] Tests exhibiting bad parial reloading behavior. NFC. · f221f13c
  Michael Kuperstein authored Nov 14, 2016
  f221f13c
- [AArch64] Split 0 vector stores into scalar store pairs. · 526c5058
  Geoff Berry authored Nov 14, 2016
  526c5058
- Revert "ARM: sort register lists by encoding in push/pop instructions." · 1b66f39c
  Tim Northover authored Nov 14, 2016
  1b66f39c
- ARM: sort register lists by encoding in push/pop instructions. · e908ea84
  Tim Northover authored Nov 14, 2016
  e908ea84
- [PPC] Add intrinsic mapping to the xscvhpsp instruction · a435e07d
  Sean Fertile authored Nov 14, 2016
  a435e07d
- AMDGPU/SI: Support data types other than V4f32 in image intrinsics · 8236fe10
  Changpeng Fang authored Nov 14, 2016
  8236fe10
- [X86] Adding reproducer for pr30981 · 35bb7fda
  Zvi Rackover authored Nov 14, 2016
  35bb7fda
- [Hexagon] Remove unsafe load instructions that affect Stack Slot Coloring · d428cf8b
  Sumanth Gundapaneni authored Nov 14, 2016
  d428cf8b
- [PPC] add intrinsics for vec extract exp/significand and vec test data class. · adda5b2d
  Sean Fertile authored Nov 14, 2016
  adda5b2d
- [X86] Cleanup 'x' and 'y' mnemonic suffixes for vcvtpd2dq/vcvttpd2dq/vcvtpd2ps... · b8596e4d
  Craig Topper authored Nov 14, 2016
  b8596e4d
- [AVX-512] Remove and autoupgrade masked dword/qword variable shift intrinsics... · 353e59b6
  Craig Topper authored Nov 14, 2016
  353e59b6
Nov 13, 2016
- [ValueTracking] recognize even more variants of smin/smax · cfcc42bd
  Sanjay Patel authored Nov 13, 2016
  cfcc42bd
- AMDGPU: Implement SGPR spilling with scalar stores · dc45274d
  Matt Arsenault authored Nov 13, 2016
  dc45274d
- revert commit r286761, some builds failed on Win platforms · e2399f9e
  Igor Breger authored Nov 13, 2016
  e2399f9e
- [X86][SSE] Add zero lower 32-bits test case for PR30845 · 055c09c1
  Simon Pilgrim authored Nov 13, 2016
  055c09c1
- [X86][AVX512] Add masked VPMOZX test case for PR26762 · 8f7c5612
  Simon Pilgrim authored Nov 13, 2016
  8f7c5612
- [X86][SSE] Add additional test case for PR30845 · ce59a536
  Simon Pilgrim authored Nov 13, 2016
  ce59a536
- [X86][AVX512] Removing llvm x86 intrinsics for _mm_mask_move_{ss|sd} intrinsics. · c09b3769
  Ayman Musa authored Nov 13, 2016
  c09b3769
- [X86][AVX512] Add patterns for all variants of VMOVSS/VMOVSD instructions. · 46af8f9c
  Ayman Musa authored Nov 13, 2016
  46af8f9c
- [AVX-512] Add unmasked intrinsics for variable shifts of dwords and qwords. · 43e97649
  Craig Topper authored Nov 13, 2016
  43e97649
- [AMDGPU] Add f16 support (VI+) · f86e4b72
  Konstantin Zhuravlyov authored Nov 13, 2016
  f86e4b72