Commits · eb31c3c5cbedf3fc74b9db73419847b14cbe45e6 · Roger Ferrer / llvm-epi · GitLab

Feb 10, 2021
- Revert rGe1172959226689a "[X86][AVX] canonicalizeLaneShuffleWithRepeatedOps -... · eb31c3c5
  Simon Pilgrim authored Feb 10, 2021
  eb31c3c5
- [WebAssembly] Enable loop unrolling · 9d81ccc0
  Sam Parker authored Feb 10, 2021
  9d81ccc0
- [AArch64][GlobalISel] Fold selects fed by G_PTR_ADD · 7eee8585
  Jessica Paquette authored Feb 09, 2021
  7eee8585
Feb 09, 2021
- [AArch64][GlobalISel] Allow vector load legalization into 128-bit-wide types · 0e85d634
  Jessica Paquette authored Feb 08, 2021
  0e85d634
- [CUDA, NVPTX] Allow targeting sm_86 GPUs. · 2aa01cce
  Artem Belevich authored Feb 03, 2021
  2aa01cce
- AMDGPU: Fix verifier error with argument passed in CSR SGPR · f4ca6d82
  Matt Arsenault authored Feb 04, 2021
  f4ca6d82
- GlobalISel: Fix using wrong calling convention for callees · b72a2365
  Matt Arsenault authored Feb 08, 2021
  b72a2365
- [RISCV] Make the min and max vector width command line options more consistent... · 18ff7e04
  Craig Topper authored Feb 09, 2021
  18ff7e04
- [RISCV] Remove SRO* and SLO* instructions from bitmanip. · fd5adae0
  Craig Topper authored Feb 09, 2021
  fd5adae0
- Revert "[ObjC][ARC] Use operand bundle 'clang.arc.rv' instead of explicitly" · de1966e5
  Nico Weber authored Feb 09, 2021
  de1966e5
- [X86][SSE] foldShuffleOfHorizOp - add SHUFPS v4f32 handling · 89d9ff82
  Simon Pilgrim authored Feb 09, 2021
  89d9ff82
- [DAGCombine] Do not remove masking argument to FP16_TO_FP for some targets · a5222aa0
  Nemanja Ivanovic authored Feb 09, 2021
  a5222aa0
- [RISCV] Fix shared libs build · f6e4b9fc
  Nemanja Ivanovic authored Feb 09, 2021
  f6e4b9fc
- [AVR] Fix global references to function symbols · 2ccb9417
  Dylan McKay authored Feb 09, 2021
  2ccb9417
- [RISCV] Use whole register load/store for generic load/store. · a2d19bad
  Hsiangkai Wang authored Feb 09, 2021
  a2d19bad
- Revert "[CostModel] Remove VF from IntrinsicCostAttributes" · 92028062
  Jinsong Ji authored Feb 09, 2021
  92028062
- [SPARC] Recognize and handle the %lm(sym) operator · 45e33e8b
  LemonBoy authored Feb 08, 2021
  45e33e8b
Feb 08, 2021
- [RISCV] Initial support of LoopVectorizer for RISC-V Vector. · a5b07a22
  Hsiangkai Wang authored Jan 27, 2021
  a5b07a22
- AMDGPU: Stop adding stack passed wide arguments to call conv handler · bcf723b2
  Matt Arsenault authored Feb 07, 2021
  bcf723b2
- [NVPTX][NewPM] Re-enable NVVMReflectPass · e84a4650
  Arthur Eubanks authored Feb 08, 2021
  e84a4650
- [ARM] One-off identity shuffle · 0c7e044a
  David Green authored Feb 08, 2021
  0c7e044a
- [AArch64][GlobalISel] Support the 'returned' parameter attribute. · ec41ed5b
  Amara Emerson authored Feb 03, 2021
  ec41ed5b
- [AArch64] Use '//' as comment string for MSVC assembly · 71c29b4c
  Martin Storsjö authored Feb 08, 2021
  71c29b4c
- [RISCV] Use _COMMUTABLE fma pseudos for fixed vectors. · b49aaed8
  Craig Topper authored Feb 08, 2021
  b49aaed8
- [RISCV] Add support for splat fixed length build_vectors using RVV. · 8d8cafa3
  Craig Topper authored Feb 08, 2021
  8d8cafa3
- [RISCV] Add support for fixed vector FMA. · b8d719fb
  Craig Topper authored Feb 08, 2021
  b8d719fb
- [RISCV] Add initial support for converting fixed vectors to scalable vectors... · a719b667
  Craig Topper authored Feb 08, 2021
  a719b667
- [RISCV] Make scalable vector FMA commutable for register allocation. · b7b4f4cb
  Craig Topper authored Feb 08, 2021
  b7b4f4cb
- [RISCV] Use SplatPat/SplatPat_simm5 to handle PseudoVMV_V_X_/PseudoVMV_V_I_ selection as well. · cc2c45dc
  Craig Topper authored Feb 08, 2021
  cc2c45dc
- [AMDGPU] Use named unified buffer format constant. NFC. · a4b1df8a
  Jay Foad authored Feb 08, 2021
  
  a4b1df8a
- [AArch64AsmParser] Fix type-limits warning for VectorIndex. · 981a38ba
  Sander de Smalen authored Feb 08, 2021
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- AArch64: use a constpool for blockaddress(...) on MachO · c93d50dd
  Tim Northover authored Feb 08, 2021
  c93d50dd
- [RISCV] Use std::make_tuple to make some toolchains happy again · eb8c27c6
  Mikael Holmen authored Feb 08, 2021
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- [CodeGen][AArch64] Add TargetInstrInfo hook to modify the TailDuplicateSize default threshold · cd880442
  Nicholas Guy authored Jan 28, 2021
  cd880442
- [AMDGPU]: Fixes an invalid clamp selection pattern. · f89f6d1e
  Thomas Symalla authored Feb 02, 2021
  f89f6d1e
- [ARM] Make v2f64 scalar_to_vector legal · 11e415dc
  David Green authored Feb 08, 2021
  11e415dc
- [AMDGPU][MC] Corrected error position for invalid dim modifiers · 05433a8d
  Dmitry Preobrazhensky authored Feb 08, 2021
  05433a8d
- [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands · 168ccc8e
  Dmitry Preobrazhensky authored Feb 08, 2021
  168ccc8e
- [RISCV] Support the scalable-vector fadd reduction intrinsic · b46aac12
  Fraser Cormack authored Feb 02, 2021
  b46aac12
- [WebAssembly] Fix multiclass template parameter types. NFC. · db5abfbb
  Simon Pilgrim authored Feb 08, 2021
  db5abfbb