Commits · eb55735073d53f7816b9a4080e6f54dfeda5ae50 · Roger Ferrer / llvm-epi · GitLab

Oct 02, 2020
- Reland [AlwaysInliner] Update BFI when inlining · eb557350
  Arthur Eubanks authored Sep 25, 2020
  eb557350
- Revert "[AlwaysInliner] Update BFI when inlining" · 9b8c0b8b
  Arthur Eubanks authored Oct 02, 2020
  9b8c0b8b
- [AlwaysInliner] Update BFI when inlining · b1bf2466
  Arthur Eubanks authored Sep 25, 2020
  b1bf2466
- Revert rG3d14a1e982ad27 - "[InstCombine] recognizeBSwapOrBitReverseIdiom -... · 0364721e
  Simon Pilgrim authored Oct 02, 2020
  0364721e
- [InstCombine] Add trunc(bswap(trunc/zext(x))) vector tests · d0dd7cad
  Simon Pilgrim authored Oct 02, 2020
  
  d0dd7cad
- [MemCpyOpt] Regnerate test checks (NFC) · 64c54c54
  Nikita Popov authored Oct 01, 2020
  
  64c54c54
- Revert "[WebAssembly] Emulate v128.const efficiently" · 432e4e56
  Stella Stamenova authored Oct 02, 2020
  432e4e56
- [InstCombine] recognizeBSwapOrBitReverseIdiom - support for 'partial' bswap patterns (PR47191) · 3d14a1e9
  Simon Pilgrim authored Oct 02, 2020
  3d14a1e9
- [AArch64] Generate dot for v16i8 sum reduction to i32 · f1925949
  Vinay Madhusudan authored Oct 02, 2020
  f1925949
- Fix interaction between stack alignment and inline-asm stack clash protection · f2c6bfa3
  serge-sans-paille authored Jul 23, 2020
  f2c6bfa3
- [Statepoints][ISEL] visitGCRelocate: chain to current DAG root. · 7b19cd06
  Denis Antrushin authored Oct 01, 2020
  7b19cd06
- [SLP] Add test where reduction result is used in PHI. · bb448a24
  Florian Hahn authored Oct 02, 2020
  bb448a24
- [InstCombine] Add partial bswap vector test from D88578 · 53fb9d06
  Simon Pilgrim authored Oct 02, 2020
  
  53fb9d06
- [PhaseOrdering] Add test that requires peeling before vectorization. · 6481a764
  Florian Hahn authored Sep 29, 2020
  6481a764
- [GVN LoadPRE] Add test to show an opportunty. · 8ae1369f
  Serguei Katkov authored Oct 02, 2020
  8ae1369f
- [InstCombine] Add some basic vector bswap tests · ec07ae2a
  Simon Pilgrim authored Oct 02, 2020
  ec07ae2a
- [InstCombine] Add partial bswap test from D88578 · 670e60c0
  Simon Pilgrim authored Oct 02, 2020
  
  670e60c0
- [ARM] Prevent constants from iCmp instruction from being hoisted if part of a min(max()) pattern · f7c0e2b8
  Meera Nakrani authored Oct 02, 2020
  f7c0e2b8
- [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV. · 067add7b
  Hsiangkai Wang authored Jul 28, 2020
  067add7b
- Fix limit behavior of dynamic alloca · 9573c9f2
  serge-sans-paille authored Sep 30, 2020
  9573c9f2
- [yaml2obj][elf2yaml] - Add a support for the `EntSize` field for `SHT_HASH` sections. · 5829dc92
  Georgii Rymar authored Oct 01, 2020
  5829dc92
- [WebAssembly] Emulate v128.const efficiently · 542523a6
  Thomas Lively authored Oct 02, 2020
  542523a6
- [AArch64] Omit SEH directives for the epilogue if none are needed · afb4e0f2
  Martin Storsjö authored Oct 01, 2020
  afb4e0f2
- [gvn] Handle a corner case w/vectors of non-integral pointers · f29645e7
  Philip Reames authored Oct 01, 2020
  f29645e7
- CodeGen: Fix livein calculation in MachineBasicBlock splitAt · 5136f474
  Carl Ritson authored Oct 02, 2020
  5136f474
- [PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC. · c4690b00
  Esme-Yi authored Oct 02, 2020
  c4690b00
- [OpenMP] Add Missing Runtime Call for Globalization Remarks · 82453e75
  Joseph Huber authored Sep 30, 2020
  82453e75
- [XCOFF] Enable -fdata-sections on AIX · 78a9e62a
  jasonliu authored Oct 01, 2020
  78a9e62a
- [memcpyopt] Conservatively handle non-integral pointers · bb034464
  Philip Reames authored Oct 01, 2020
  bb034464
- [AArch64][SVE] Add lowering for llvm fabs · aab6f7db
  Muhammad Asif Manzoor authored Oct 01, 2020
  aab6f7db
- Fix a bug in memset formation with vectors of non-integral pointers · de3cb954
  Philip Reames authored Oct 01, 2020
  de3cb954
- [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs · 5402d11b
  Jessica Paquette authored Sep 30, 2020
  5402d11b
- [AArch64][GlobalISel] Use emitTestBit in selection for G_BRCOND · 8e8664e5
  Jessica Paquette authored Oct 01, 2020
  8e8664e5
- [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP. · 017b8715
  Amara Emerson authored Oct 01, 2020
  017b8715
Oct 01, 2020
- [AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal. · e28c5899
  Amara Emerson authored Oct 01, 2020
  
  e28c5899
- [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support. · a97e97fa
  Amara Emerson authored Oct 01, 2020
  
  a97e97fa
- Revert "[AArch64][GlobalISel] Make <8 x s8> shifts legal." · 9a2b3bbc
  Amara Emerson authored Oct 01, 2020
  9a2b3bbc
- [AArch64][GlobalISel] Make <8 x s8> shifts legal. · 8071c2f5
  Amara Emerson authored Oct 01, 2020
  
  8071c2f5
- [AArch64][GlobalISel] Merge G_SHL, G_ASHR and G_LSHR legalizer rules together. · 9f6acb13
  Amara Emerson authored Oct 01, 2020
  9f6acb13
- [AArch64][GlobalISel] Use custom legalization for G_TRUNC for v8i8 vectors. · 73457536
  Amara Emerson authored Sep 23, 2020
  73457536