Commits · ebe0be9ca46f4c856d42b86354073e492c1eeda8 · Roger Ferrer / llvm-epi · GitLab

Jun 07, 2013
- Vincent says the element is at most once in the vector, so we don't need a full std::remove. · ebe0be9c
  Benjamin Kramer authored Jun 07, 2013
  ebe0be9c
- Use isxdigit. · 8d477dc0
  Rafael Espindola authored Jun 07, 2013
  8d477dc0
- Fix a typo in asm string of BP* family of instructions. With this fix · 158d8069
  Roman Divacky authored Jun 07, 2013
  158d8069
- Support OpenBSD's native frame protection conventions. · aad6c244
  Rafael Espindola authored Jun 07, 2013
  aad6c244
- R600: Fix a potential iterator invalidation issue. · a857fe11
  Benjamin Kramer authored Jun 07, 2013
  a857fe11
- R600: Remove an extra break in R600OptimizeVectorRegisters.cpp · 931bb768
  Vincent Lejeune authored Jun 07, 2013
  931bb768
- Fold variable that's only used in assert into the assert. · f0ec1994
  Benjamin Kramer authored Jun 07, 2013
  f0ec1994
- Correct wrong register in this example, pointed out by Baoshan Pang. · e0a607e3
  Duncan Sands authored Jun 07, 2013
  e0a607e3
- Don't cache the instruction and register info from the TargetMachine, because · 5e7656bf
  Bill Wendling authored Jun 07, 2013
  5e7656bf
- Don't cache the instruction and register info from the TargetMachine, because · ead89ef6
  Bill Wendling authored Jun 07, 2013
  ead89ef6
- Don't cache the instruction and register info from the TargetMachine, because · f5358213
  Bill Wendling authored Jun 07, 2013
  f5358213
- Don't cache the instruction and register info from the TargetMachine, because · 90bee83c
  Bill Wendling authored Jun 07, 2013
  90bee83c
- Don't cache the instruction and register info from the TargetMachine, because · 4a7a408e
  Bill Wendling authored Jun 07, 2013
  4a7a408e
- [objc-arc] Ensure that the cfg path count does not overflow when we multiply... · 9e7261c8
  Michael Gottesman authored Jun 07, 2013
  9e7261c8
- Don't cache the instruction and register info from the TargetMachine, because · f95178e6
  Bill Wendling authored Jun 07, 2013
  f95178e6
- Don't cache the instruction info and register info objects. · 496dc33b
  Bill Wendling authored Jun 07, 2013
  496dc33b
- DIBuilder: No functionality change. · 60711600
  Manman Ren authored Jun 07, 2013
  60711600
- ARM sched model: Use the right resources for DIV · c5893da3
  Arnold Schwaighofer authored Jun 07, 2013
  c5893da3
- ARM sched model: Add VFP div instruction on Swift · 5f0a2ce5
  Arnold Schwaighofer authored Jun 07, 2013
  5f0a2ce5
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · a30936a3
  Arnold Schwaighofer authored Jun 07, 2013
  a30936a3
- [Sparc]: Use cmp instruction instead of subcc to compare integers. · dc82ac0d
  Venkatraman Govindaraju authored Jun 07, 2013
  dc82ac0d
- Simplify code. No functionality change. · 96ff4d6d
  Jakub Staszak authored Jun 06, 2013
  96ff4d6d
- R600: Rewrite an awkward loop in R600MachineScheduler · 0030362e
  Vincent Lejeune authored Jun 06, 2013
  0030362e
- Jeffrey Yasskin volunteered to benchmark the vectorizer on -O2 or -Os when... · 99e529ea
  Nadav Rotem authored Jun 06, 2013
  99e529ea
- Fix break in r183446 - helps to increment the iterator in a loop · b272a753
  David Blaikie authored Jun 06, 2013
  b272a753
Jun 06, 2013
- Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift" · e5f6a8f6
  Arnold Schwaighofer authored Jun 06, 2013
  e5f6a8f6
- Debug Info: simplify parameter ordering preservation · 36d5d2f0
  David Blaikie authored Jun 06, 2013
  36d5d2f0
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · cfe830dc
  Arnold Schwaighofer authored Jun 06, 2013
  cfe830dc
- ARM sched model: Add integer VFP/SIMD instructions on Swift · eac54473
  Arnold Schwaighofer authored Jun 06, 2013
  eac54473
- Re-apply "Use IRBuilder instead of ConstantInt methods." with the fixed issues. · bddea11b
  Jakub Staszak authored Jun 06, 2013
  bddea11b
- ARM sched model: Add integer load/store instructions on Swift · dff8e4c4
  Arnold Schwaighofer authored Jun 06, 2013
  dff8e4c4
- ARM sched model: Add integer arithmetic instructions on Swift · 41a7b068
  Arnold Schwaighofer authored Jun 06, 2013
  41a7b068
- ARM sched model: Cortex A9 - More InstRW sched resources · 57142859
  Arnold Schwaighofer authored Jun 06, 2013
  57142859
- ARM sched model: Add branch thumb instructions · f1395b69
  Arnold Schwaighofer authored Jun 06, 2013
  f1395b69
- ARM sched model: Add branch thumb2 instructions · 10ccc99c
  Arnold Schwaighofer authored Jun 06, 2013
  10ccc99c
- ARM sched model: Add branch instructions · 91d4ee37
  Arnold Schwaighofer authored Jun 06, 2013
  91d4ee37
- ARM sched model: Add preload thumb2 instructions · 57727977
  Arnold Schwaighofer authored Jun 06, 2013
  57727977
- ARM sched model: Add preload instructions · 1b413304
  Arnold Schwaighofer authored Jun 06, 2013
  1b413304
- Teach llvm-objdump with the -macho parser how to use the data in code table · 273ae01b
  Kevin Enderby authored Jun 06, 2013
  273ae01b
- ARM sched model: Add more ALU and CMP thumb instructions · 654649dd
  Arnold Schwaighofer authored Jun 06, 2013
  654649dd