Commits · ec5c93d3a0b57a1246f2e24de011413af950becf · Roger Ferrer / llvm-epi · GitLab

Jun 08, 2016
- [ARM] MSR instructions implicitly set CPSR · b3378e2f
  Oliver Stannard authored Jun 08, 2016
  b3378e2f
- [mips] Add a proper file header in MipsFastISel.cpp · a9e5154d
  Vasileios Kalintiris authored Jun 08, 2016
  a9e5154d
- [Hexagon] Modify HexagonExpandCondsets to handle subregisters · b16882dd
  Krzysztof Parzyszek authored Jun 08, 2016
  b16882dd
- [ARM] Remove redundant check. NFC · 0781d10a
  Diana Picus authored Jun 08, 2016
  0781d10a
- Avoid copies of std::strings and APInt/APFloats where we only read from it · 46e38f36
  Benjamin Kramer authored Jun 08, 2016
  46e38f36
- [AVX512] Fix cvtusi2sd instruction Opcode, it should be 0x7B instead of 0x2A. · 982e4003
  Igor Breger authored Jun 08, 2016
  982e4003
- [AArch64][RegisterBankInfo] Use the generic implementation of copyCost. · a4ac7cda
  Quentin Colombet authored Jun 08, 2016
  a4ac7cda
- [RegisterBankInfo] Add a size argument for the cost of copy. · cfbdee23
  Quentin Colombet authored Jun 08, 2016
  cfbdee23
Jun 07, 2016
- AMDGPU: Add amdgpu-ps-wqm-outputs function attributes · c00e03b8
  Nicolai Haehnle authored Jun 07, 2016
  c00e03b8
- Revert "Differential Revision: http://reviews.llvm.org/D20557 " · 538d09d0
  Eric Christopher authored Jun 07, 2016
  538d09d0
- [stack-protection] Add support for MSVC buffer security check · 22bfa832
  Etienne Bergeron authored Jun 07, 2016
  22bfa832
- Revert r272045 since GCC doesn't know how to compile it. · 8b61759c
  Krzysztof Parzyszek authored Jun 07, 2016
  8b61759c
- [Hexagon] Modify HexagonExpandCondsets to handle subregisters · 8424280e
  Krzysztof Parzyszek authored Jun 07, 2016
  8424280e
- Differential Revision: http://reviews.llvm.org/D20557 · a70216f1
  Wei Ding authored Jun 07, 2016
  a70216f1
- Reapply [AArch64] Fix isLegalAddImmediate() to return true for valid negative values. · 486f49cc
  Geoff Berry authored Jun 07, 2016
  486f49cc
- [ARM] Accept conditional versions of BXNS and BLXNS · 8de5f24d
  Oliver Stannard authored Jun 07, 2016
  8de5f24d
- [X86][SSE] Add general lowering of nontemporal vector loads (fixed bad merge) · 35c06a02
  Simon Pilgrim authored Jun 07, 2016
  35c06a02
- [X86][SSE] Add general lowering of nontemporal vector loads · 9a89623b
  Simon Pilgrim authored Jun 07, 2016
  9a89623b
- [Thumb-1] Add optimized constant materialization for integers [256..512) · b101383f
  James Molloy authored Jun 07, 2016
  b101383f
- [AVX512] Fix load opcode for fast isel. · 61e62859
  Igor Breger authored Jun 07, 2016
  61e62859
- [PowerPC] Support multiple return values with fast isel · 6b0634b3
  Ulrich Weigand authored Jun 07, 2016
  6b0634b3
- [X86][SSE] Improved blend+zero target shuffle combining to use combined shuffle mask directly · ca1da1bf
  Simon Pilgrim authored Jun 07, 2016
  ca1da1bf
- [ARM] Shrink post-indexed LDR and STR to LDM/STM · 53298a18
  James Molloy authored Jun 07, 2016
  53298a18
- [ARM] Transform LDMs into writeback form to save code size · 75afc951
  James Molloy authored Jun 07, 2016
  75afc951
- [ARM] Incorrect relocation type for Thumb2 B<cond>.w · 353a2286
  Peter Smith authored Jun 07, 2016
  353a2286
- [AVX512] Allow avx2 and sse41 nontemporal load intrinsics to select EVEX... · 2f90c1fe
  Craig Topper authored Jun 07, 2016
  2f90c1fe
- [AVX512] Remove unnecessary mayLoad, mayStore, hasSidEffects flags from... · e1cac15f
  Craig Topper authored Jun 07, 2016
  e1cac15f
- [AVX512] Add NoVLX to a couple patterns that have VLX equivalents. Ordering of... · 0fcf9256
  Craig Topper authored Jun 07, 2016
  0fcf9256
- ARM: correct TLS access on WoA · 532dcbc2
  Saleem Abdulrasool authored Jun 07, 2016
  532dcbc2
- ARM: clang-format a couple of switches, add comments · ce4eee49
  Saleem Abdulrasool authored Jun 07, 2016
  ce4eee49
- ARM: normalise space in the patterns · 0cd0cb99
  Saleem Abdulrasool authored Jun 07, 2016
  0cd0cb99
Jun 06, 2016
- AMDGPU: Add function for getting instruction size · 02458c2d
  Matt Arsenault authored Jun 06, 2016
  02458c2d
- AMDGPU: Fix constantexpr addrspacecasts · 3b2e2a59
  Matt Arsenault authored Jun 06, 2016
  3b2e2a59
- [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. · 13548776
  Artem Tamazov authored Jun 06, 2016
  13548776
- [KNL] Fix UMULO lowering. · edafb059
  Igor Breger authored Jun 06, 2016
  edafb059
- Remove dead function with incredibly broken assert. · f21beb2c
  Benjamin Kramer authored Jun 06, 2016
  f21beb2c
- [NFC] Silence gcc warning (-Wsign-compare) · 6e7d5467
  Filipe Cabecinhas authored Jun 06, 2016
  6e7d5467
- [AVX512] Add PALIGNR shuffle lowering for v32i16 and v16i32. · 143446d5
  Craig Topper authored Jun 06, 2016
  143446d5
Jun 05, 2016
- [X86][XOP] Added VPERMIL2PD/VPERMIL2PS raw mask decoding for target shuffle combines · 64c6de45
  Simon Pilgrim authored Jun 05, 2016
  64c6de45
- [X86][XOP] Added VPERMIL2PD/VPERMIL2PS as a target shuffle type · 478295da
  Simon Pilgrim authored Jun 05, 2016
  478295da