Commits · f003d9ff95eecb2cd84b8c46f1ad9485a597c161 · Roger Ferrer / llvm-epi · GitLab

Nov 30, 2017
- [ARM GlobalISel] Bail out for byval · f003d9ff
  Diana Picus authored Nov 30, 2017
  f003d9ff
- [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output · 93ef1458
  Francis Visoiu Mistrih authored Nov 30, 2017
  93ef1458
- [MC] Function stack size section. · f77b4d2f
  Sean Eveson authored Nov 30, 2017
  f77b4d2f
- Support generic lowering of vector bswap · 24386867
  Serge Guelton authored Nov 30, 2017
  24386867
- [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes · 3e5987cf
  Simon Pilgrim authored Nov 30, 2017
  3e5987cf
- [SystemZ] Bugfix in adjustSubwordCmp. · b9a24675
  Jonas Paulsson authored Nov 30, 2017
  b9a24675
- [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type. · a495744d
  Craig Topper authored Nov 30, 2017
  a495744d
- [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers. · 321a8b9b
  Craig Topper authored Nov 30, 2017
  321a8b9b
- AMDGPU: Allow negative MUBUF vaddr for gfx9 · caf0ed4d
  Matt Arsenault authored Nov 30, 2017
  caf0ed4d
- First step towards more human-friendly PPC assembler output: · 4b1acff9
  Joerg Sonnenberger authored Nov 29, 2017
  4b1acff9
Nov 29, 2017
- [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint to... · cf461a0a
  Craig Topper authored Nov 29, 2017
  cf461a0a
- [WebAssembly] Fix fptoui lowering bounds · 580c102a
  Dan Gohman authored Nov 29, 2017
  580c102a
- [Hexagon] Remove HexagonISD::PACKHL · f4dcc42e
  Krzysztof Parzyszek authored Nov 29, 2017
  f4dcc42e
- [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION) · 4d2c7034
  Simon Pilgrim authored Nov 29, 2017
  4d2c7034
- [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes · 87034cb4
  Simon Pilgrim authored Nov 29, 2017
  87034cb4
- [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions scheduler classes · 36be852c
  Simon Pilgrim authored Nov 29, 2017
  36be852c
- [ARM][DAG] Revert Disable post-legalization store merge for ARM · bafaa53c
  Nirav Dave authored Nov 29, 2017
  bafaa53c
- [Power9] add more tests for D38287; NFC · 76fe1006
  Zaara Syeda authored Nov 29, 2017
  76fe1006
- [ARM GlobalISel] Fix selecting G_BRCOND · 863b5b05
  Diana Picus authored Nov 29, 2017
  863b5b05
- [ARM] Add support for armv7e-m to the .arch directive · 9ea2eaeb
  Oliver Stannard authored Nov 29, 2017
  9ea2eaeb
- [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended. · aab3ef76
  Sean Fertile authored Nov 29, 2017
  aab3ef76
- AMDGPU: Use stricter regexes for add instructions · 9a7e29ae
  Matt Arsenault authored Nov 29, 2017
  9a7e29ae
- AMDGPU: Select DS insts without m0 initialization · 3f71c0e3
  Matt Arsenault authored Nov 29, 2017
  3f71c0e3
- [X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization. · fbf7b3bf
  Craig Topper authored Nov 29, 2017
  fbf7b3bf
- [X86] Add test cases for fptosi v16f32->v16i8/v16i16 to show scalarization. · 8261c8c0
  Craig Topper authored Nov 29, 2017
  8261c8c0
- [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of... · 88ffb5d4
  Craig Topper authored Nov 28, 2017
  88ffb5d4
- [X86] Regenerate avx512-schedule test. · 3f749c2d
  Craig Topper authored Nov 28, 2017
  3f749c2d
- AMDGPU: Enable IPRA · 607a7566
  Matt Arsenault authored Nov 28, 2017
  607a7566
- [X86] Tag CLFLUSHOPT with same scheduling behaviour as CLFLUSH · b9aa93cb
  Simon Pilgrim authored Nov 28, 2017
  b9aa93cb
- [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal() · 40c5cbfb
  Daniel Sanders authored Nov 28, 2017
  40c5cbfb
- [X86] Add CLFLUSHOPT schedule tests · a675071b
  Simon Pilgrim authored Nov 28, 2017
  a675071b
- [X86] Test clflushopt intrinsic on 32 and 64-bit targets · c6c2103e
  Simon Pilgrim authored Nov 28, 2017
  c6c2103e
Nov 28, 2017
- [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG,... · 76664651
  Daniel Sanders authored Nov 28, 2017
  76664651
- [aarch64][globalisel] Add missing tests from r319216 · 7b361b50
  Daniel Sanders authored Nov 28, 2017
  7b361b50
- [PowerPC] Allow tail calls of fastcc functions from C CallingConv functions. · e200016e
  Sean Fertile authored Nov 28, 2017
  e200016e
- [X86] In lowerVectorShuffleAsElementInsertion, if were able to find a scalar... · dd429562
  Craig Topper authored Nov 28, 2017
  dd429562
- [Hexagon] Make sure to zero-extend bytes before building a vector · 081e458e
  Krzysztof Parzyszek authored Nov 28, 2017
  081e458e
- [mir] Print/Parse both MOLoad and MOStore when they occur together. · 17d277b7
  Daniel Sanders authored Nov 28, 2017
  17d277b7
- AMDGPU: Add num spilled s/vgprs to metadata · 06ae4ec7
  Konstantin Zhuravlyov authored Nov 28, 2017
  06ae4ec7
- [CodeGen] Print register names in lowercase in both MIR and debug output · 9d7bb0cb
  Francis Visoiu Mistrih authored Nov 28, 2017
  9d7bb0cb