Commits · f0093e45c4fb5a765ddf94367ddd675f3efb6bc3 · Roger Ferrer / llvm-epi · GitLab

Sep 15, 2017
- Revert r313343 "[X86] PR32755 : Improvement in CodeGen instruction selection for LEAs." · 534bfbd3
  Hans Wennborg authored Sep 15, 2017
  534bfbd3
- [X86] PR32755 : Improvement in CodeGen instruction selection for LEAs. · 908c8b37
  Jatin Bhateja authored Sep 15, 2017
  908c8b37
Aug 29, 2017
- [LSR] Fix Shadow IV in case of integer overflow · bb1d0108
  Max Kazantsev authored Aug 29, 2017
  bb1d0108
- [NFC] Fix indents in test · f2e017b0
  Max Kazantsev authored Aug 29, 2017
  f2e017b0
- [NFC] Refactor ShadowIV test to use FileCheck · 03407da2
  Max Kazantsev authored Aug 29, 2017
  03407da2
Aug 24, 2017
- [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes · 540a39ad
  Evgeny Astigeevich authored Aug 24, 2017
  540a39ad
Aug 07, 2017
- Reapply fix PR23384 (part 3 of 3) r304824 (was reverted in r305720). · c6752906
  Evgeny Stupachenko authored Aug 07, 2017
  c6752906
Aug 04, 2017
- [SCEV] Preserve NSW information for sext(subtract). · 56dca4e3
  Amara Emerson authored Aug 04, 2017
  56dca4e3
- Fix PR33514 · 38197c66
  Evgeny Stupachenko authored Aug 04, 2017
  38197c66
Jul 28, 2017
- Remove the obsolete offset parameter from @llvm.dbg.value · abe04759
  Adrian Prantl authored Jul 28, 2017
  abe04759
Jul 06, 2017
- [LSR] Narrow search space by filtering non-optimal formulae with the same ScaledReg and Scale. · 90707394
  Wei Mi authored Jul 06, 2017
  90707394
Jun 19, 2017
- Revert r304824 "Fix PR23384 (part 3 of 3)" · ca69fc1c
  Hans Wennborg authored Jun 19, 2017
  ca69fc1c
- [SCEV] Teach SCEVExpander to expand BinPow · 35b2a18e
  Max Kazantsev authored Jun 19, 2017
  35b2a18e
Jun 06, 2017
- Fix PR23384 (part 3 of 3) · 3b882915
  Evgeny Stupachenko authored Jun 06, 2017
  3b882915
Jun 04, 2017
- [X86] Replace 'REQUIRES: x86' in tests with 'REQUIRES: x86-registered-target'... · 2b54baeb
  Craig Topper authored Jun 04, 2017
  2b54baeb
May 27, 2017
- [SCEVExpander] Try harder to avoid introducing inttoptr · 090f1959
  Keno Fischer authored May 27, 2017
  090f1959
May 26, 2017
- Re-enable "[SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start" · 41450329
  Max Kazantsev authored May 26, 2017
  41450329
May 24, 2017
- Revert "[SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start" · 183863fc
  Diana Picus authored May 24, 2017
  183863fc
- [SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start · 13e016bf
  Max Kazantsev authored May 24, 2017
  13e016bf
May 18, 2017
- [LSR] Call canonicalize after we generate a new Formula in GenerateTruncates. Fix PR33077. · 8848c1e3
  Wei Mi authored May 18, 2017
  8848c1e3
Apr 20, 2017
- ARM: handle post-indexed NEON ops where the offset isn't the access width. · 8b1240b0
  Tim Northover authored Apr 20, 2017
  8b1240b0
Apr 07, 2017
- Turn on -addr-sink-using-gep by default. · 5fba1e53
  Eli Friedman authored Apr 06, 2017
  5fba1e53
Mar 21, 2017
- AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel · 3dbeefa9
  Matt Arsenault authored Mar 21, 2017
  3dbeefa9
Mar 04, 2017
- Set option enabling LSR alternative way to resolve complex solution to false. · d6aa0d02
  Evgeny Stupachenko authored Mar 04, 2017
  d6aa0d02
Feb 22, 2017
- [LSR] Canonicalize formula and put recursive Reg related with current loop in ScaledReg. · 74d5a90f
  Wei Mi authored Feb 22, 2017
  74d5a90f
Feb 21, 2017
- The patch introduces new way of narrowing complex (>UINT16 variants) solutions. · 9909872e
  Evgeny Stupachenko authored Feb 21, 2017
  9909872e
Feb 16, 2017
- [LSR] Prevent formula with SCEVAddRecExpr type of Reg from Sibling loops · 493fb266
  Wei Mi authored Feb 16, 2017
  493fb266
Feb 14, 2017
- [LSR] Pointers with different address spaces are considered incompatible. · ece84cd1
  Mikael Holmen authored Feb 14, 2017
  ece84cd1
Feb 11, 2017
- The patch fixes r294821 · 5f3d9b6c
  Evgeny Stupachenko authored Feb 11, 2017
  5f3d9b6c
- Fix PR23384 (under "-lsr-insns-cost" option) · fe6f548d
  Evgeny Stupachenko authored Feb 11, 2017
  fe6f548d
- [LSR] Recommit: Allow formula containing Reg for SCEVAddRecExpr related with outerloop. · 8f20e63a
  Wei Mi authored Feb 11, 2017
  8f20e63a
Feb 08, 2017
- LSR: Check atomic instruction pointer operands · cb3fa37c
  Matt Arsenault authored Feb 08, 2017
  cb3fa37c
Jan 30, 2017
- LSR: Don't drop address space when type doesn't match · 1f2ca663
  Matt Arsenault authored Jan 30, 2017
  1f2ca663
Jan 23, 2017
- This test apparently requires an x86 target and is failing on numerous · d501b189
  Chandler Carruth authored Jan 23, 2017
  d501b189
Jan 15, 2017
- [PM] Clean up the testing for IVUsers, especially with the new PM. · 0952750f
  Chandler Carruth authored Jan 15, 2017
  0952750f
Jan 13, 2017
- [LoopStrengthReduce] Don't bother rewriting PHIs in catchswitch blocks · bba17390
  David Majnemer authored Jan 13, 2017
  bba17390
Nov 15, 2016
- Revert r286999 which caused buildbot test failures. Some testcases need to be made target specific. · 37c4aaaf
  Wei Mi authored Nov 15, 2016
  37c4aaaf
- [LSR] Allow formula containing Reg for SCEVAddRecExpr related with outerloop. · 7ccf7651
  Wei Mi authored Nov 15, 2016
  7ccf7651
Nov 09, 2016
- [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb. · 0ee3ec2f
  Alexandros Lamprineas authored Nov 09, 2016
  0ee3ec2f
Oct 12, 2016
- Fix testcases failing after r284036 · 3cb5ffeb
  Krzysztof Parzyszek authored Oct 12, 2016
  3cb5ffeb